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21. 发明申请

US20120174979A1 Efficiency in Antireflective Coating Layers for Solar Cells 有权
标题翻译：太阳能电池抗反射涂层的效率
公开(公告)号：US20120174979A1
公开(公告)日：2012-07-12
申请号：US13416354
申请日：2012-03-09
申请人： Harold J. Hovel , Rainer K. Krause , Zhengwen Li , Huilong Zhu
发明人： Harold J. Hovel , Rainer K. Krause , Zhengwen Li , Huilong Zhu
IPC分类号： H01L31/0224 , H01L31/0232
CPC分类号： G02B1/113 , H01L31/02168 , H01L31/022425 , H01L31/068 , H01L31/1868 , Y02E10/547 , Y02P70/521
摘要： A solar cell includes a substrate having an N-region and a P-region, a first anti-reflective layer disposed on the substrate, a metallic contact disposed on the first anti-reflective layer, a second anti-reflective layer disposed on the first anti-reflective layer and the metallic contact, and a region partially defined by the first anti-reflective layer and the second anti-reflective layer having diffused metallic contact material operative to form a conductive path to the substrate through the first anti-reflective layer, the metallic contact, and the second anti-reflective layer.
摘要翻译：太阳能电池包括具有N区和P区的衬底，设置在衬底上的第一抗反射层，设置在第一抗反射层上的金属触点，设置在第一抗反射层上的第二抗反射层抗反射层和金属接触，以及由第一抗反射层和第二抗反射层局部限定的区域，其具有扩散的金属接触材料，其可操作以通过第一抗反射层形成到衬底的导电路径，金属触点和第二抗反射层。

22. 发明申请

US20110317324A1 Solar Module with Overheat Protection 有权
标题翻译：具有过热保护功能的太阳能电池组件
公开(公告)号：US20110317324A1
公开(公告)日：2011-12-29
申请号：US13166842
申请日：2011-06-23
申请人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Krause , Zhengwen Li , Kevin S. Petrarca , Gerd Pfeiffer , Kevin Prettyman , Carl J. Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Krause , Zhengwen Li , Kevin S. Petrarca , Gerd Pfeiffer , Kevin Prettyman , Carl J. Radens , Brian C. Sapp
IPC分类号： H02H5/04
CPC分类号： H02H7/20 , H01L31/02021 , H02H5/047 , Y02E10/50
摘要： A photovoltaic module (10) with a plurality of solar cells (20) interconnected in serial and/or parallel arrangement within the module (10) is equipped with an overheat protection system (30) for suppressing damages of the photovoltaic module (10) due to defects of the solar cells (20). The overheat protection system (30) comprises a heat sensor (32) which is thermally coupled to a solar cell (20). The heat sensor (32) is physically integrated into an electrical switch (34, 36, 38) which is electrically connected to said solar cell (20).
摘要翻译：具有在模块（10）内以串联和/或并联布置互连的多个太阳能电池（20）的光伏模块（10）装备有过热保护系统（30），用于抑制光伏模块（10）的损坏涉及太阳能电池的缺陷（20）。过热保护系统（30）包括热耦合到太阳能电池（20）的热传感器（32）。热传感器（32）物理地集成在电连接到所述太阳能电池（20）的电开关（34,36,38）中。

23. 发明申请

US20110100443A1 Photovoltaic solar cell device manufacture 失效
标题翻译：光伏太阳能电池器件制造
公开(公告)号：US20110100443A1
公开(公告)日：2011-05-05
申请号：US12916236
申请日：2010-10-29
申请人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Carl Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Carl Radens , Brian C. Sapp
IPC分类号： H01L31/06 , H01L31/0236
CPC分类号： H01L31/022425 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method for manufacturing a photovoltaic solar cell device includes the following. A p-n junction having a first doping density is formed. Formation of the p-n junction is enhanced by introducing a second doping density to form high doped areas for a dual emitter application. The high doped areas are defined by a masking process integrated with the formation of the p-n junction, resulting in a mask pattern of the high doped areas. A metallization of the high doped areas occurs in accordance with the mask pattern of the high doped areas.
摘要翻译：光伏太阳能电池器件的制造方法包括以下。形成具有第一掺杂密度的p-n结。通过引入第二掺杂密度以形成用于双发射器应用的高掺杂区域来增强p-n结的形成。高掺杂区域由与p-n结的形成集成的掩模工艺限定，产生高掺杂区域的掩模图案。根据高掺杂区域的掩模图案发生高掺杂区域的金属化。

24. 发明申请

US20100304519A1 METHOD OF FABRICATING SOLAR CELL CHIPS 审中-公开
标题翻译：制造太阳能电池的方法
公开(公告)号：US20100304519A1
公开(公告)日：2010-12-02
申请号：US12849448
申请日：2010-08-03
申请人： Hans-Juergen Eickelmann , Michael Haag , Harold J. Hovel , Rainer Klaus Krause , Markus Schmidt , Xiaoyan Shao , Steven Erik Steen
发明人： Hans-Juergen Eickelmann , Michael Haag , Harold J. Hovel , Rainer Klaus Krause , Markus Schmidt , Xiaoyan Shao , Steven Erik Steen
IPC分类号： H01L31/18 , H01L21/027 , H01L21/283
CPC分类号： H01L31/068 , H01L31/02168 , H01L31/022425 , H01L31/022433 , H01L31/1804 , H01L31/1868 , Y02E10/547 , Y02P70/521
摘要： A method of fabricating solar cell chips. The method includes creating an integrated circuit chip process route for fabricating integrated circuit chips using integrated circuit wafers in an integrated circuit fabrication facility; creating a solar cell process route for fabricating solar cells using solar cell wafers in the integrated circuit fabrication facility; releasing integrated circuit chip wafers and solar cell wafers into tool queues of tools of the an integrated circuit fabrication facility; and processing the solar cell wafers on at least some tools of the integrated circuit fabrication facility used to process the integrated circuit wafers. Also the process used to fabricate the solar cell chips.
摘要翻译：制造太阳能电池芯片的方法。该方法包括在集成电路制造设备中创建用于使用集成电路晶片制造集成电路芯片的集成电路芯片工艺路线; 在集成电路制造设备中创建使用太阳能电池晶片制造太阳能电池的太阳能电池工艺路线; 将集成电路芯片晶片和太阳能电池晶片释放到集成电路制造设备的工具的工具队列中; 以及在用于处理集成电路晶片的集成电路制造设备的至少一些工具上处理太阳能电池晶片。也是制造太阳能电池芯片的过程。

25. 发明申请

US20100083999A1 TANDEM NANOFILM SOLAR CELLS JOINED BY WAFER BONDING 有权
标题翻译： TANDEM NANOFILM太阳能电池由WAFER BONDING加入
公开(公告)号：US20100083999A1
公开(公告)日：2010-04-08
申请号：US12246511
申请日：2008-10-07
申请人： Harold J. Hovel
发明人： Harold J. Hovel
IPC分类号： H01L31/042
CPC分类号： H01L31/0725 , B82Y20/00 , H01L31/022433 , H01L31/0236 , H01L31/02366 , H01L31/035236 , H01L31/053 , H01L31/0547 , H01L31/0687 , H01L31/0693 , H01L31/18 , H01L31/1884 , Y02E10/52 , Y02E10/544
摘要： An energy conversion device comprises at least two thin film photovoltaic cells fabricated separately and joined by wafer bonding. The cells are arranged in a hierarchical stack of decreasing order of their energy bandgap from top to bottom. Each of the thin film cells has a thickness in the range from about 0.5 μm to about 10 μm. The photovoltaic cell stack is mounted upon a thick substrate composed of a material selected from silicon, glass, quartz, silica, alumina, ceramic, metal, graphite, and plastic. Each of the interfaces between the cells comprises a structure selected from a tunnel junction, a heterojunction, a transparent conducting oxide, and an alloying metal grid; and the top surface and/or the lower surface of the energy conversion device may contain light-trapping means.
摘要翻译：能量转换装置包括至少两个单独制造并通过晶片接合连接的薄膜光伏电池。这些单元以从顶部到底部的能量带隙的递减顺序排列成分层堆叠。每个薄膜电池的厚度在约0.5μm至约10μm的范围内。光电池堆叠安装在由硅，玻璃，石英，二氧化硅，氧化铝，陶瓷，金属，石墨和塑料中选择的材料构成的厚基板上。单元之间的每个接口包括选自隧道结，异质结，透明导电氧化物和合金金属栅格的结构; 并且能量转换装置的顶表面和/或下表面可以包含光捕获装置。

26. 发明授权

US07682846B2 Single and double-gate pseudo-FET devices for semiconductor materials evaluation 失效
标题翻译：用于半导体材料评估的单栅极和双栅极伪FET器件
公开(公告)号：US07682846B2
公开(公告)日：2010-03-23
申请号：US12169190
申请日：2008-07-08
申请人： Harold J. Hovel , Thermon E. McKoy
发明人： Harold J. Hovel , Thermon E. McKoy
IPC分类号： H01L21/36
CPC分类号： H01L29/66772 , G01R31/2648 , H01L21/28512 , H01L21/84 , H01L22/14 , H01L22/34 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/66742 , H01L29/78645 , H01L29/78648 , H01L29/78654 , H01L29/78687 , H01L31/08 , H01L2924/3011
摘要： Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes. In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode. Light of broad spectrum or specific wavelength may be used to alter electrical carrier densities in the region between the electrodes to further analyze the electrical properties of the material, or alternatively, the device can be used as a detector of light having a wavelength shorter than the bandgap wavelength of the Si surface.
摘要翻译：公开了几种方法和结构，用于确定绝缘体上硅（SOI）晶片的电性能以及诸如应变硅：硅/锗：绝缘体（SSGOI）晶片之类的晶片的替代形式。通过在晶片表面上沉积电极并测量使用这些电极的电流 - 电压行为，所分析的电特性包括迁移率，界面态密度和氧化物电荷。在单个栅极结构中，源极和漏极位于晶片表面上，埋入的绝缘体用作栅极氧化物，衬底用作栅电极。在双栅极结构中，在源极和漏极之间的上表面上使用氧化物，并且在该氧化物的顶部上使用附加的金属层作为第二栅电极。可以使用宽光谱或特定波长的光来改变电极之间的区域中的电载体密度，以进一步分析材料的电学性质，或者替代地，该器件可以用作波长短于 Si表面的带隙波长。

27. 发明授权

US07288446B2 Single and double-gate pseudo-FET devices for semiconductor materials evaluation 失效
标题翻译：用于半导体材料评估的单栅极和双栅极伪FET器件
公开(公告)号：US07288446B2
公开(公告)日：2007-10-30
申请号：US11219919
申请日：2005-09-06
申请人： Harold J. Hovel , Thermon E. McKoy
发明人： Harold J. Hovel , Thermon E. McKoy
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/66772 , G01R31/2648 , H01L21/28512 , H01L21/84 , H01L22/14 , H01L22/34 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/66742 , H01L29/78645 , H01L29/78648 , H01L29/78654 , H01L29/78687 , H01L31/08 , H01L2924/3011
摘要： Several methods and structures are disclosed for determining electrical properties of silicon-on-insulator (SOI) wafers and alternate versions of such wafers such as strained silicon:silicon/germanium:-on-insulator (SSGOI) wafers. The analyzed electrical properties include mobilities, interface state densities, and oxide charge by depositing electrodes on the wafer surface and measuring the current-voltage behavior using these electrodes, In a single gate structure, the source and drain electrodes reside on the wafer surface and the buried insulator acts as the gate oxide, with the substrate acting as the gate electrode. In a double gate structure, an oxide is used on the upper surface between the source and drain electrodes and an additional metal layer is used on top of this oxide to act as a second gate electrode. Light of broad spectrum or specific wavelength may be used to alter electrical carrier densities in the region between the electrodes to further analyze the electrical properties of the material, or alternatively, the device can be used as a detector of light having a wavelength shorter than the bandgap wavelength of the Si surface.
摘要翻译：公开了几种方法和结构，用于确定绝缘体上硅（SOI）晶片的电性能以及诸如应变硅：硅/锗：绝缘体（SSGOI）晶片之类的晶片的替代形式。分析的电气特性包括迁移率，界面态密度和通过在晶片表面上沉积电极并测量使用这些电极的电流 - 电压行为的氧化物电荷。在单个栅极结构中，源极和漏极驻留在晶片表面上，并且掩埋绝缘体用作栅极氧化物，其中衬底用作栅电极。在双栅极结构中，在源极和漏极之间的上表面上使用氧化物，并且在该氧化物的顶部上使用附加的金属层作为第二栅电极。可以使用宽光谱或特定波长的光来改变电极之间的区域中的电载体密度，以进一步分析材料的电学性质，或者替代地，该器件可以用作波长短于 Si表面的带隙波长。

28. 发明授权

US4708883A Annealing process 失效
标题翻译：退火过程
公开(公告)号：US4708883A
公开(公告)日：1987-11-24
申请号：US821139
申请日：1986-01-23
申请人： Harold J. Hovel , Thomas F. Kuech
发明人： Harold J. Hovel , Thomas F. Kuech
IPC分类号： C23C14/06 , C23C14/58 , H01L21/265 , H01L21/324 , B05D3/06
CPC分类号： C23C14/0617 , C23C14/58 , C23C14/5806 , C23C14/5893 , H01L21/2654 , H01L21/3245
摘要： An ion implantation annealing source for a controlled excess of the most volatile element of a multielement compound semiconductor whereby the source is provided with interstices and contains the most volatile element of the multielement semiconductor; and process of ion implantation employing the annealing source.
摘要翻译：一种离子注入退火源，用于多元素化合物半导体中最易挥发的元素受控过量，其中源极具有间隙并且包含多元素半导体中最易挥发的元素; 以及使用退火源的离子注入工艺。

29. 发明授权

US08878055B2 Efficient nanoscale solar cell and fabrication method 有权
标题翻译：高效纳米级太阳能电池及其制造方法
公开(公告)号：US08878055B2
公开(公告)日：2014-11-04
申请号：US12852991
申请日：2010-08-09
申请人： Keith E. Fogel , William S. Graham , Jeehwan Kim , Harold J. Hovel , Devendra K. Sadana , Katherine L. Saenger
发明人： Keith E. Fogel , William S. Graham , Jeehwan Kim , Harold J. Hovel , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L31/00 , H01L31/052 , H01L31/0236 , H01L31/0352
CPC分类号： H01L31/0527 , H01L31/02366 , H01L31/03529 , H01L31/056 , Y02E10/52
摘要： A photovoltaic device and method include a substrate layer having a plurality of structures including peaks and troughs formed therein. A continuous photovoltaic stack is conformally formed over the substrate layer and extends over the peaks and troughs. The photovoltaic stack has a thickness of less than one micron and is configured to transduce incident radiation into current flow.
摘要翻译：光电器件和方法包括具有多个结构的衬底层，包括形成在其中的峰和谷。连续的光伏堆叠保形地形成在衬底层上并且延伸超过峰和谷。光伏堆叠具有小于1微米的厚度，并且被配置为将入射辐射转换成电流。

30. 发明授权

US08441042B2 BEOL compatible FET structure 有权
标题翻译： BEOL兼容FET结构
公开(公告)号：US08441042B2
公开(公告)日：2013-05-14
申请号：US12561827
申请日：2009-09-17
申请人： Christy S. Tyberg , Katherine L. Saenger , Jack O. Chu , Harold J. Hovel , Robert L. Wisnieff , Kerry Bernstein , Stephen W. Bedell
发明人： Christy S. Tyberg , Katherine L. Saenger , Jack O. Chu , Harold J. Hovel , Robert L. Wisnieff , Kerry Bernstein , Stephen W. Bedell
IPC分类号： H01L21/76
CPC分类号： H01L23/5226 , H01L23/53271 , H01L27/124 , H01L27/1248 , H01L2924/0002 , H01L2924/00
摘要： This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.
摘要翻译：本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。

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