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    • 27. 发明授权
    • Deadlock avoidance in a bus fabric
    • 总线架构中的死锁避免
    • US07882296B2
    • 2011-02-01
    • US12330515
    • 2008-12-09
    • David G. Reed
    • David G. Reed
    • G06F13/36G06F13/00
    • G06F13/4036G06F13/1642
    • Circuits, apparatus, and methods for avoiding deadlock conditions in a bus fabric. One exemplary embodiment provides an address decoder for determining whether a received posted request is a peer-to-peer request. If it is, the posted request is sent as a non-posted request. A limit on the number of pending non-posted requests is maintained and not exceed, such that deadlock is avoided. Another exemplary embodiment provides an arbiter that tracks a number of pending posted requests. When the number pending posted requests reaches a predetermined or programmable level, a Block Peer-to-Peer signal is sent to the arbiter's clients, again avoiding deadlock.
    • 用于避免总线结构中死锁状况的电路,装置和方法。 一个示例性实施例提供了一种地址解码器,用于确定接收到的发送的请求是否是对等请求。 如果是,发布的请求将作为未发布的请求发送。 对待处理的未发布的请求数量的限制将保持不超过,从而避免死锁。 另一示例性实施例提供了一种仲裁器,其跟踪多个未决发布的请求。 当等待发送的请求数量达到预定或可编程的级别时,块对等信号被发送给仲裁者的客户端,同时避免死锁。
    • 29. 发明申请
    • MEMORY CONTROLLER-ADAPTIVE 1T/2T TIMING CONTROL
    • 内存控制器 - 自适应1T / 2T时序控制
    • US20090276597A1
    • 2009-11-05
    • US12502628
    • 2009-07-14
    • David G. Reed
    • David G. Reed
    • G06F12/00G11C7/00
    • G06F13/1684
    • Circuits, methods, and apparatus that adaptively control 1T and 2T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as an additional memory interface, each having a number of address and control lines. The address and control lines of the redundant memory interface may be individually enabled and disabled. If a line in the additional interface is enabled, it and its corresponding line in the first interface drive a reduced load and may operate at the higher 1T data rate. If a line in the additional interface is disabled, then its corresponding line in the first interface drives a higher load and may operate at the slower 2T data rate. In either case, the operating speed of the interface may also be considered in determining whether each line operates with 1T or 2T timing.
    • 自适应地控制1T和2T定时的存储器控​​制器接口的电路,方法和装置。 本发明的实施例提供了第一存储器接口以及附加存储器接口,每个存储器接口具有多个地址和控制线。 可以单独启用和禁用冗余存储器接口的地址和控制线。 如果附加接口中的一条线路被使能,那么其​​第一个接口中的线路和相应的线路将减少负载,并可能以较高的1T数据速率工作。 如果附加接口中的一条线路被禁用,则其第一个接口中的相应线路驱动较高的负载,并且可能以较慢的2T数据速率运行。 在任一种情况下,在确定每条线路是否以1T或2T定时运行时,也可考虑接口的工作速度。