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21. 发明授权

US07054136B2 Controlled ESR low inductance multilayer ceramic capacitor 有权
标题翻译：受控ESR低电感多层陶瓷电容器
公开(公告)号：US07054136B2
公开(公告)日：2006-05-30
申请号：US10446464
申请日：2003-05-28
申请人： Andrew P. Ritter , John L. Galvagni
发明人： Andrew P. Ritter , John L. Galvagni
IPC分类号： H01G4/228 , H01G4/20
CPC分类号： H01G4/30 , H01G4/2325
摘要： A multilayer ceramic capacitor assembly capable of exhibiting low high-frequency inductance and a controlled equivalent series resistance (ESR) while maintaining a useful capacitance value includes respective pluralities of first and second electrode elements interleaved to form a stack. Controlled ESR is achieved either through inclusion of specific types of materials or through alteration of the shape of various component parts. A resistive material may be used in typical end terminations, via terminations, electrode elements or connective tab structures. Additionally, the dielectric may be made lossy so as to enhance resistivity without overly affecting device capacitance. Still further, an additional layer of resistive material may be added to an outer device surface to connect filled-via terminations to end terminations or radial resistive prints may be used to only partially fill the vias. Finally, various electrode element configurations, such as flat plate, serpentine, mesh, L-, O- or U-shaped patterns, may be employed.
摘要翻译：能够表现出低的高频电感和受控的等效串联电阻（ESR）同时保持有用的电容值的多层陶瓷电容器组件包括相互交织以形成叠层的多个第一和第二电极元件。通过包含特定类型的材料或通过改变各种组分部件的形状来实现受控ESR。电阻材料可用于典型的端接端子，通过端子，电极元件或连接片结构。此外，电介质可以是有损的，以便增强电阻率而不会过度影响器件电容。此外，可以将附加的电阻材料层添加到外部器件表面以将填充通孔端子连接到端部端子，或者径向电阻印刷可用于仅部分填充通孔。最后，可以采用诸如平板，蛇形，网状，L-，O-或U形图案的各种电极元件结构。

22. 发明授权

US06982863B2 Component formation via plating technology 有权
公开(公告)号：US06982863B2
公开(公告)日：2006-01-03
申请号：US10409036
申请日：2003-04-08
申请人： John L. Galvagni , Jason MacNeal , Andrew P. Ritter , Robert Heistand, II , Sriram Dattaguru
发明人： John L. Galvagni , Jason MacNeal , Andrew P. Ritter , Robert Heistand, II , Sriram Dattaguru
IPC分类号： H01G4/228 , H01G4/32
CPC分类号： H01G4/232 , Y10T29/43 , Y10T29/435
摘要： Improved terminations, interconnection techniques, and inductive element features for multilayer electronic components are formed in accordance with disclosed plating techniques. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such plated termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed varying width internal electrode tabs and additional anchor tab portions. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. The combination of electrode tabs and anchor tabs may be exposed in respective arrangements to form generally discoidal portions of plated material. Such plated material may ultimately form generally round portions of ball limiting metallurgy (BLM) to which solder balls may be reflowed. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and materials may be employed in the formation of the subject self-determining plated terminations and inductive components.

23. 发明授权

US09666366B2 Method of making multi-layer electronic components with plated terminations 有权
公开(公告)号：US09666366B2
公开(公告)日：2017-05-30
申请号：US10951972
申请日：2004-09-28
申请人： Andrew P. Ritter , Robert Heistand, II , John L. Galvagni , Sriram Dattaguru
发明人： Andrew P. Ritter , Robert Heistand, II , John L. Galvagni , Sriram Dattaguru
IPC分类号： H01G4/008 , H01C1/14 , H01C7/00 , H01C7/10 , H01G4/005 , H01G4/012 , H01G4/228 , H01G4/232 , H01G4/30 , C25D5/02 , H05K3/02 , C23C18/16 , C23C18/32 , C23C18/38 , C23C18/48 , C23C28/02 , C25D7/00 , H01G4/12 , H05K3/40
CPC分类号： H01G4/30 , C23C18/1651 , C23C18/1653 , C23C18/32 , C23C18/38 , C23C18/48 , C23C28/021 , C23C28/023 , C25D3/56 , C25D5/02 , C25D5/34 , C25D7/00 , H01C1/14 , H01C7/008 , H01C7/10 , H01C17/28 , H01F41/04 , H01G4/005 , H01G4/008 , H01G4/012 , H01G4/06 , H01G4/12 , H01G4/228 , H01G4/232 , H05K3/02 , H05K3/403 , H05K2201/09709 , Y10T29/417 , Y10T29/42 , Y10T29/43 , Y10T29/435 , Y10T29/49002 , Y10T29/49099 , Y10T29/49101
摘要： Improved method steps for making a multilayer electronic components are disclosed. Monolithic components are formed with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. Electrodes and insulating substrates are provided in an interleaved arrangement and selected portions of the electrodes are exposed along selected edges of the substrates. Anchor tabs, which are not in direct contact with the electrodes and offer additional nucleation points for plated structures, may also optionally be provided and exposed in some embodiments. Termination material is then plated to the exposed portions of the electrodes and optional anchor tabs, such as via electroless and/or electrochemical processes, until exposed portions of selected groups thereof are connected.

24. 发明授权

US07414857B2 Multilayer ceramic capacitor with internal current cancellation and bottom terminals 有权
标题翻译：具有内部电流消除和底部端子的多层陶瓷电容器
公开(公告)号：US07414857B2
公开(公告)日：2008-08-19
申请号：US11588104
申请日：2006-10-26
申请人： Andrew P. Ritter , John L. Galvagni
发明人： Andrew P. Ritter , John L. Galvagni
IPC分类号： H05H5/00
CPC分类号： H01G4/232 , H01C1/148 , H01C7/18 , H01G2/065 , H01G4/30 , H05K1/0231 , H05K1/113 , H05K2201/0792
摘要： Low inductance capacitors include electrodes that are arranged among dielectric layers and oriented such that the electrodes are substantially perpendicular to a mounting surface. Vertical electrodes are exposed along a device periphery to determine where termination lands are formed, defining a narrow and controlled spacing between the lands that is intended to reduce the current loop area, thus reducing the component inductance. Further reduction in current loop area and thus component equivalent series inductance (ESL) may be provided by interdigitated terminations. Terminations may be formed by various electroless plating techniques, and may be directly soldered to circuit board pads. Terminations may also be located on “ends” of the capacitors to enable electrical testing or to control solder fillet size and shape. Two-terminal devices may be formed as well as devices with multiple terminations on a given bottom (mounting) surface of the device. Terminations may also be formed on the top surface (opposite a designated mounting surface) and may be a mirror image, reverse-mirror image, or different shape relative to the bottom surface.
摘要翻译：低电感电容器包括布置在电介质层之间并定向为使得电极基本上垂直于安装表面的电极。垂直电极沿着器件外围露出，以确定在哪里形成终端焊盘，限定了焊盘之间的狭窄和可控的间距，用于减小电流环路面积，从而降低了元件电感。可以通过叉指式终端来提供电流回路面积和部件等效串联电感（ESL）的进一步减小。端接可以通过各种无电镀技术形成，并且可以直接焊接到电路板焊盘。端子也可以位于电容器的“端部”上，以实现电气测试或控制焊接圆角尺寸和形状。可以在设备的给定的底部（安装）表面上形成两端子器件以及具有多个端子的器件。端子也可以形成在顶表面（与指定的安装表面相对）上，并且可以是镜像，反向镜像或相对于底表面的不同形状。

25. 发明授权

US07177137B2 Plated terminations 有权
标题翻译：电镀端接
公开(公告)号：US07177137B2
公开(公告)日：2007-02-13
申请号：US10818951
申请日：2004-04-06
申请人： Andrew P. Ritter , Robert Heistand, II , John L. Galvagni , Sriram Dattaguru , Jeffrey A. Horn , Richard A. Ladew
发明人： Andrew P. Ritter , Robert Heistand, II , John L. Galvagni , Sriram Dattaguru , Jeffrey A. Horn , Richard A. Ladew
IPC分类号： H01G4/228
CPC分类号： H01G4/012 , H01G4/232 , H01G4/30 , H01L2924/01029 , Y10T29/42 , Y10T29/43 , Y10T29/435
摘要： A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of internal electrode elements and a plurality of internal anchor tabs. Portions of the internal electrode elements and anchor tabs are exposed along the periphery of the electronic component in one or more aligned columns. Each exposed portion is within a predetermined distance from other exposed portions in a given column such that bridged terminations may be formed by depositing one or more plated termination materials over selected of the respectively aligned columns. Internal anchor tabs may be provided and exposed in prearranged relationships with other exposed conductive portions to help nucleate metallized plating material along the periphery of a device. External anchor tabs or lands may be provided to form terminations that extend to top and/or bottom surfaces of the device. Selected of the conductive elements may be formed by a finite volume percentage of ceramic material for enhanced durability, and external lands may be thicker than internal conductive elements and/or may also be embedded in top and/or bottom component surfaces. A variety of potential internal electrode configurations are possible including ones configured for orientation-insensitive component mounting and for high density peripheral termination interdigitated capacitors.
摘要翻译：多层电子部件包括与多个内部电极元件和多个内部固定突片交错的多个电介质层。内部电极元件和锚定片的部分沿着电子元件的外围在一个或多个对齐的列中露出。每个暴露部分在与给定列中的其它暴露部分预定距离内，使得桥接端接可以通过在选定的分别对准的柱上沉积一个或多个电镀终止材料而形成。可以提供内部锚定突片并以与其它暴露的导电部分的预定关系暴露，以帮助沿着装置的周边使金属化电镀材料成核。可以提供外部锚定片或平台以形成延伸到装置的顶部和/或底部表面的终端。选择的导电元件可以由有限体积百分比的陶瓷材料形成，以增强耐久性，并且外部焊盘可以比内部导电元件厚，和/或也可以嵌入在顶部和/或底部部件表面中。各种潜在的内部电极配置是可能的，包括被配置用于定向不敏感元件安装和用于高密度外围端接叉指电容器的构造。

26. 发明授权

US07170737B2 Window via capacitor 有权
标题翻译：通过电容窗
公开(公告)号：US07170737B2
公开(公告)日：2007-01-30
申请号：US11338037
申请日：2006-01-23
申请人： Jason MacNeal , John L. Galvagni , Andrew P. Ritter
发明人： Jason MacNeal , John L. Galvagni , Andrew P. Ritter
IPC分类号： H01G4/228 , H01G4/06
CPC分类号： H01G4/232 , H01G4/30
摘要： A window via capacitor comprises a stacked multilayer configuration of at least one bottom layer, a plurality of first and second layers, a transition layer and a cover layer. An alternative window via capacitor comprises a stacked configuration of a bottom window layer, a bottom transition layer, a plurality of first and second layers, followed by a top window layer and a top cover layer. Each first and second layer is preferably characterized by a sheet of dielectric material with a respective first or second electrode plate provided thereon. Adjacent first and second electrode plates form opposing active capacitor plates in the multilayer configuration. Portions of each first and second electrode plate extend to and are exposed on selected side portions of the periphery of the window via capacitor. Electrode portions of each transition layer are aligned in respective similar locations to the first and second electrode plates such that peripheral terminations can connect selected electrode portions of a first polarity together and selected portions of the opposing polarity together. In some embodiments, the connection of peripheral terminations to the electrode portions of the transition layer collect the two opposing terminations onto a single planar surface. Window vias may then be formed through windows provided in the cover layers to effect low inductance electrical connection to the active components of the window via capacitor. Solder balls may also be applied to such window vias to yield a capacitor compatible with BGA mounting technology.
摘要翻译：窗口通孔电容器包括至少一个底层，多个第一和第二层，过渡层和覆盖层的堆叠多层结构。通过电容器的替代窗口包括底部窗口层，底部过渡层，多个第一和第二层的层叠构造，其后是顶部窗口层和顶部覆盖层。每个第一层和第二层的特征在于一层电介质材料，其上设有相应的第一或第二电极板。相邻的第一和第二电极板在多层结构中形成相对的有源电容器板。每个第一和第二电极板的部分经由电容器延伸到窗口的周边的选定的侧部并且暴露在窗的周边的选定的侧部。每个过渡层的电极部分在与第一和第二电极板的各自相似的位置中对准，使得外围终端可以将选定的第一极性的电极部分连接在一起并将相对极性的选定部分连接在一起。在一些实施例中，外围终端与过渡层的电极部分的连接将两个相对的终端收集在单个平面表面上。然后可以通过设置在覆盖层中的窗口形成窗口通孔，以通过电容器实现与窗户的有源部件的低电感电连接。焊球也可以应用于这种窗口通孔，以产生与BGA安装技术兼容的电容器。

27. 发明授权

US07067172B2 Component formation via plating technology 有权
标题翻译：通过电镀技术形成组件
公开(公告)号：US07067172B2
公开(公告)日：2006-06-27
申请号：US10829639
申请日：2004-04-22
申请人： Andrew P. Ritter , John L. Galvagni , Jason MacNeal , Robert Heistand, II , Sriram Dattaguru
发明人： Andrew P. Ritter , John L. Galvagni , Jason MacNeal , Robert Heistand, II , Sriram Dattaguru
IPC分类号： B05D5/12 , H01G7/00 , C25D5/02
CPC分类号： H01G4/232 , Y10T29/43 , Y10T29/435
摘要： Improved terminations, interconnection techniques, and inductive element features for multilayer electronic components are formed in accordance with disclosed plating techniques. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such plated termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed varying width internal electrode tabs and additional anchor tab portions. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. The combination of electrode tabs and anchor tabs may be exposed in respective arrangements to form generally discoidal portions of plated material. Such plated material may ultimately form generally round portions of ball limiting metallurgy (BLM) to which solder balls may be reflowed. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and materials may be employed in the formation of the subject self-determining plated terminations and inductive components.
摘要翻译：根据公开的电镀技术形成改进的端接，互连技术和用于多层电子部件的电感元件特征。单片组件设置有电镀端接，从而消除或大大简化了对典型厚膜端接条的需要。这种电镀终端技术消除了许多典型的终端问题，并且能够以更细的间距实现更高数量的终端，这对于较小的电子部件可能是特别有益的。受电镀的终端由暴露的变化宽度的内部电极片和附加的锚定片部分引导和锚定。这种锚定片可以相对于芯片结构位于内部或外部，以使附加的金属化电镀材料成核。电极片和锚定片的组合可以以各自的布置暴露以形成电镀材料的大致盘形部分。这种电镀材料最终可以形成通常圆球形限制冶金（BLM）的圆形部分，焊球可以回流到该部分。所公开的技术可以与多个单片多层组件一起使用，包括交错电容器，多层电容器阵列和集成无源组件。各种不同的电镀技术和材料可用于形成受试者自确定的电镀终端和电感组分。

28. 发明授权

US06898070B2 Transmission line capacitor 失效
标题翻译：传输线电容
公开(公告)号：US06898070B2
公开(公告)日：2005-05-24
申请号：US10733848
申请日：2003-12-11
申请人： George Korony , Andrew P. Ritter
发明人： George Korony , Andrew P. Ritter
IPC分类号： H01G4/12 , H01G2/00 , H01G2/06 , H01G4/02 , H01G4/08 , H01G4/18 , H01G4/228 , H01G4/232 , H01G4/30 , H01G4/35 , H01G4/38
CPC分类号： H01G4/38 , H01G4/232 , H01G4/30
摘要： A transmission line capacitor includes at least two side-by-side capacitor portions spaced apart between a separating portion all contained in a single monolithic body. Such transmission line capacitors provide specific capacitor functionality for parallel transmission lines in a printed circuit board environment, while also maintaining a desired impedance value between the transmission paths. The transmission line capacitors offer both biasing functionality for blocking undesired DC voltages as well as AC coupling functionality for passing AC voltage signals with preserved data integrity. A first embodiment may be formed with a dielectric material having a relatively low dielectric constant, allowing high capacitor “height” with fixed spacing between distinct capacitive structures. Another embodiment may be formed with a relative high K dielectric and then slotted with an air gap between capacitive structures. Yet another embodiment may be formed with a relatively high K dielectric material, and with a relatively low K material provided in between capacitive structures. A still further embodiment concerns a transmission line capacitor design formed with high K and low K dielectric materials punched into a monolithic thin-film device.
摘要翻译：传输线电容器包括至少两个并排电容器部分，其间分离在全部包含在单个整体中的分离部分。这样的传输线电容器为印刷电路板环境中的并行传输线提供特定的电容器功能，同时还在传输路径之间保持期望的阻抗值。传输线电容器提供用于阻止不期望的直流电压的偏置功能以及用于传递具有保持的数据完整性的交流电压信号的交流耦合功能。第一实施例可以由具有相对低的介电常数的电介质材料形成，允许在不同的电容结构之间具有固定间隔的高电容器“高度”。另一个实施例可以用相对高的K电介质形成，然后与电容结构之间的气隙开槽。另一个实施例可以用相对高的K电介质材料形成，并且具有设置在电容结构之间的相对低的K材料。又一实施例涉及用高K和低K电介质材料冲压成单片薄膜器件形成的传输线电容器设计。

29. 发明授权

US5629578A Integrated composite acoustic transducer array 失效
标题翻译：集成复合声换能器阵列
公开(公告)号：US5629578A
公开(公告)日：1997-05-13
申请号：US406601
申请日：1995-03-20
申请人： Stephen R. Winzer , Paul J. Caldwell , Natarajan Shankar , Tushar K. Shah , Keith Bridger , Andrew P. Ritter
发明人： Stephen R. Winzer , Paul J. Caldwell , Natarajan Shankar , Tushar K. Shah , Keith Bridger , Andrew P. Ritter
IPC分类号： B06B1/06 , H01L27/20 , H01L41/08
CPC分类号： B06B1/064 , B06B1/0614 , H01L27/20
摘要： An improved transducer array includes a two-dimensional array of multilayer actuators, capable of producing very high displacement with low input voltage, integrally packaged with conditioning electronics. Preferred microcomposite actuators use multiple layers of stacked electrostrictive ceramics and conductive materials. The actuators are aligned in a two-dimensional array and can be integrated with the conditioning electronics in a variety of packaging systems. A preferred packaging system is a flexible high density interconnected multi-chip module which has the integrated circuit chips disposed in a substrate, interconnection layers disposed thereon and the multilayer composite actuators disposed on the surface of the interconnection structure. The actuators in this packaged array may be optionally addressed individually or in blocks, depending on the application intended.
摘要翻译：改进的换能器阵列包括多层致动器的二维阵列，其能够产生与调节电子器件整体封装的具有低输入电压的非常高的位移。优选的微复合致动器使用多层堆叠的电致伸缩陶瓷和导电材料。致动器以二维阵列对准，并且可以与各种包装系统中的调节电子装置集成。优选的包装系统是柔性高密度互连多芯片模块，其具有布置在基板中的集成电路芯片，布置在其上的互连层和布置在互连结构的表面上的多层复合致动器。这种封装阵列中的致动器可以根据应用的需要而被单独地或以块的方式任意寻址。

30. 发明授权

US5527480A Piezoelectric ceramic material including processes for preparation thereof and applications therefor 失效
标题翻译：压电陶瓷材料，包括其制备方法及其应用
公开(公告)号：US5527480A
公开(公告)日：1996-06-18
申请号：US60399
申请日：1987-06-11
申请人： Alex E. Bailey , Inam Jawed , Andrew P. Ritter , Audrey E. Sutherland , Stephen R. Winzer
发明人： Alex E. Bailey , Inam Jawed , Andrew P. Ritter , Audrey E. Sutherland , Stephen R. Winzer
IPC分类号： C04B35/497 , H01L41/187 , C04B35/46 , C04B35/64
CPC分类号： H01L41/187 , C04B35/497
摘要： This invention relates to new ceramic piezoelectric compositions having superior electrical properties, processes for the preparation of the new piezoelectric composition and applications for the new compositions. Specifically, a solid solution composition of 85.5-87.5 molar percent lead zinc niobate, 9.5-9.7 molar percent lead titanate and 3-5 molar percent of a barium titanate dopant or strontium titanate dopant has exhibited desirable electrical properties. This specific composition is well suited for use in a 3-1 connectivity composite, which can be used as a hydrophone. These compositions may be prepared by oxide sintering techniques utilizing extremely high purity materials, or alternatively, by a sol gel process.
摘要翻译：本发明涉及具有优异电性能的新陶瓷压电组合物，用于制备新的压电组合物的方法和新组合物的应用。具体地说，85.5-87.5摩尔％的铌酸铅锌，9.5-9.7摩尔％的钛酸铅和3-5摩尔％的钛酸钡掺杂剂或钛酸锶钛掺杂剂的固溶体组合物表现出所需的电性能。该特定组合物非常适用于可用作水听器的3-1连接复合材料。这些组合物可以通过使用极高纯度材料的氧化物烧结技术，或者通过溶胶凝胶法制备。

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