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21. 发明授权

US06875678B2 Post thermal treatment methods of forming high dielectric layers in integrated circuit devices 有权
标题翻译：在集成电路器件中形成高介电层的后热处理方法
公开(公告)号：US06875678B2
公开(公告)日：2005-04-05
申请号：US10650415
申请日：2003-08-29
申请人： Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
发明人： Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L21/318 , H01L29/51 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/02329 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02192 , H01L21/022 , H01L21/02337 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31641 , H01L21/31645 , H01L21/3185 , H01L29/513 , H01L29/517 , H01L29/518
摘要： High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.
摘要翻译：可以将设置在硅基板上的由氧化铪，氧化锆，氧化铝，氧化钇和/或其它金属氧化物和硅酸盐的层形成的高介电层氮化并通过氧化，退火或氧化和退火的组合进行后热处理以形成具有优异的迁移率和界面特性的高介电层。

22. 发明授权

US5852319A Gate electrode for semiconductor device 失效
标题翻译：半导体器件用栅电极
公开(公告)号：US5852319A
公开(公告)日：1998-12-22
申请号：US953644
申请日：1997-10-17
申请人： Young-sun Kim , Nae-in Lee , Dae-hong Ko
发明人： Young-sun Kim , Nae-in Lee , Dae-hong Ko
IPC分类号： H01L21/28 , H01L29/423 , H01L29/49 , H01L29/78 , H01L27/088
CPC分类号： H01L21/28052 , H01L29/4933 , Y10S257/90
摘要： A gate electrode in a semiconductor device comprising; a gate oxide layer formed on a semiconductor substrate, a polysilicon layer formed on the gate oxide layer, a silicide layer formed on the polysilicon layer and, a metal silicide layer formed on the silicide layer.
摘要翻译：一种半导体器件中的栅电极，包括：形成在半导体衬底上的栅极氧化层，形成在栅极氧化层上的多晶硅层，形成在多晶硅层上的硅化物层和形成在硅化物层上的金属硅化物层。

23. 发明申请

US20080272436A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080272436A1
公开(公告)日：2008-11-06
申请号：US11853187
申请日：2007-09-11
申请人： Seo-woo Nam , Young-joon Moon , Hong-jae Shin , Nae-in Lee
发明人： Seo-woo Nam , Young-joon Moon , Hong-jae Shin , Nae-in Lee
IPC分类号： H01L21/8234 , H01L27/088 , H01L21/283
CPC分类号： H01L21/823807 , H01L21/76802 , H01L21/76816 , H01L21/76829 , H01L21/76832 , H01L21/823871 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first stress film covering a first gate electrode and first source/drain areas of a first transistor area and at least a portion of a third gate electrode of an interface area, a second stress film covering a second gate electrode and second source/drain areas of a second transistor area and overlapping at least a portion of the first stress film on the third gate electrode of the interface area, and an interlayer insulating film formed on the first and the second stress film. The semiconductor device further includes a plurality of first contact holes formed through the interlayer insulating film and the first stress film in the first transistor area to expose the first gate electrode and the first source/drain areas, a plurality of second contact holes formed through the interlayer insulating film and the second stress film in the second transistor area to expose the second gate electrode and the second source/drain areas, and a third contact hole formed through the interlayer insulating film, the second stress film, and the first stress film in the interface area to expose the third gate electrode. A depth of a recessed portion of an upper side of the third gate electrode in which the third contact hole is formed is equal to or larger than a depth of a recessed portion of an upper side of the first gate electrode in which the first contact hole is formed.
摘要翻译：半导体器件包括覆盖第一栅电极的第一应力膜和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅电极的至少一部分，覆盖第二栅电极的第二应力膜和第二应力膜第二晶体管区域的源极/漏极区域，并且与界面区域的第三栅电极上的第一应力膜的至少一部分重叠，以及形成在第一和第二应力膜上的层间绝缘膜。半导体器件还包括多个通过层间绝缘膜形成的第一接触孔和第一晶体管区域中的第一应力膜，以暴露第一栅极电极和第一源极/漏极区域，形成多个第二接触孔层间绝缘膜和第二晶体管区域中的第二应力膜，以暴露第二栅电极和第二源极/漏极区，以及通过层间绝缘膜，第二应力膜和第一应力膜形成的第三接触孔暴露第三栅电极的界面区域。形成第三接触孔的第三栅电极的上侧的凹部的深度等于或大于第一栅电极的上侧的凹部的深度，其中第一接触孔形成了。

24. 发明申请

US20050037630A1 Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices 有权
标题翻译：在集成电路器件中在界面层上形成高介电层的后热处理方法
公开(公告)号：US20050037630A1
公开(公告)日：2005-02-17
申请号：US10659945
申请日：2003-09-10
申请人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
发明人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L29/51 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02329 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02192 , H01L21/022 , H01L21/02323 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3143 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31662 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.
摘要翻译：可以将通过氧化，退火，氧化，氧化，氧化，氧化，氧化钇和/或其他金属氧化物和/或硅衬底上的其它金属氧化物和硅酸盐形成的高介电层氮化和后热处理，或氧化和退火的组合以形成具有优异迁移率和界面特性的高介电层。

25. 发明授权

US5674782A Method for efficiently removing by-products produced in dry-etching 失效
标题翻译：有效去除在干蚀刻中产生的副产物的方法
公开(公告)号：US5674782A
公开(公告)日：1997-10-07
申请号：US611432
申请日：1996-03-04
申请人： Nae-in Lee , Moon-han Park , Young-wug Kim , Kwan-young Oh
发明人： Nae-in Lee , Moon-han Park , Young-wug Kim , Kwan-young Oh
IPC分类号： H01L21/02 , H01L21/28 , H01L21/3213
CPC分类号： H01L21/02071 , H01L21/28061 , H01L21/32135
摘要： A method for efficiently removing by-products produced in dry-etching a fabricated structure of a semiconductor device, particularly, a polycide structure. The method includes the steps of sequentially forming a polysilicon layer and a refractory metal silicide layer to overlie previously fabricated structures on a semiconductor substrate, dry-etching the polysilicon layer and the refractory metal silicide layer to form a patterned polysilicon layer and a patterned refractory metal silicide layer, and thermal treating the resultant structure to remove at least one kind of by-product produced in the dry-etching step at a temperature higher than the boiling point of any by-product.
摘要翻译：一种用于有效地除去在干法蚀刻半导体器件，特别是多晶硅化物结构的制造结构中产生的副产物的方法。该方法包括以下步骤：顺序地形成多晶硅层和难熔金属硅化物层以覆盖半导体衬底上先前制造的结构，干蚀刻多晶硅层和难熔金属硅化物层以形成图案化的多晶硅层和图案化的难熔金属硅化物层，并对所得结构进行热处理，以在高于任何副产物的沸点的温度下除去在干蚀刻步骤中产生的至少一种副产物。

26. 发明授权

US07494940B2 Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices 有权
标题翻译：在集成电路器件中在界面层上形成高介电层的后热处理方法
公开(公告)号：US07494940B2
公开(公告)日：2009-02-24
申请号：US11333741
申请日：2006-01-17
申请人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
发明人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
IPC分类号： H01L21/00
CPC分类号： H01L21/02329 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02192 , H01L21/022 , H01L21/02323 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3143 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31662 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.
摘要翻译：可以将通过氧化，退火，氧化，氧化，氧化，氧化，氧化钇和/或其他金属氧化物和/或硅衬底上的其它金属氧化物和硅酸盐形成的高介电层氮化和后热处理，或氧化和退火的组合以形成具有优异迁移率和界面特性的高介电层。

27. 发明申请

US20060115993A1 Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices 有权
公开(公告)号：US20060115993A1
公开(公告)日：2006-06-01
申请号：US11333741
申请日：2006-01-17
申请人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
发明人： Seok-Joo Doh , Hyung-suk Jung , Nae-in Lee , Jong-ho Lee , Yun-seok Kim
IPC分类号： H01L21/31
CPC分类号： H01L21/02329 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02192 , H01L21/022 , H01L21/02323 , H01L21/02337 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3143 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31662 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518
摘要： High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.

28. 发明授权

US06476489B1 Apparatus and manufacturing method for semiconductor device adopting NA interlayer contact structure 失效
标题翻译：采用NA层间接触结构的半导体器件的装置和制造方法
公开(公告)号：US06476489B1
公开(公告)日：2002-11-05
申请号：US09258292
申请日：1999-02-26
申请人： Bong-young Yoo , Dae-hong Ko , Nae-in Lee , Young-wook Park
发明人： Bong-young Yoo , Dae-hong Ko , Nae-in Lee , Young-wook Park
IPC分类号： H01L2348
CPC分类号： H01L23/485 , H01L21/28061 , H01L21/76805 , H01L23/5226 , H01L23/53271 , H01L29/4925 , H01L29/4933 , H01L29/4983 , H01L2924/0002 , Y10S257/905 , Y10S257/906 , Y10S257/907 , Y10S257/908 , H01L2924/00
摘要： A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.
摘要翻译：提供了采用上下导电层之间的层间接触结构的半导体器件以及采用该结构制造半导体器件的方法。下导电层包括堆叠在一起的第一导电层和第一硅化物层。上导电层包括掺杂有杂质的第二导电层和堆叠在一起的第二硅化物层。在层间接触结构中，第一和第二导电层彼此直接接触。这降低了两个导电层之间的接触电阻并改善了器件的电性能。

29. 发明授权

US06239493B1 Apparatus and manufacturing method for semiconductor device adopting an interlayer contact structure 有权
公开(公告)号：US06239493B1
公开(公告)日：2001-05-29
申请号：US09258292
申请日：1999-02-26
申请人： Bong-young Yoo , Dae-hong Ko , Nae-in Lee , Young-wook Park
发明人： Bong-young Yoo , Dae-hong Ko , Nae-in Lee , Young-wook Park
IPC分类号： H01L2348
摘要： A semiconductor device adopting an interlayer contact structure between upper and lower conductive layers and a method of manufacturing the semiconductor device adopting the structure are provided. The lower conductive layer includes a first conductive layer and a first silicide layer stacked together. The upper conductive layer includes a second conductive layer doped with impurities and a second silicide layer stacked together. In the interlayer contact structure, the first and second conductive layers are in direct contact with each other. This decreases the contact resistance between the two conductive layers and improves the electrical properties of the device.

30. 发明申请

US20070059923A1 Methods of fabricating damascene interconnection line in semiconductor devices and semiconductor devices fabricated using such methods 审中-公开
标题翻译：在使用这种方法制造的半导体器件和半导体器件中制造镶嵌互连线的方法
公开(公告)号：US20070059923A1
公开(公告)日：2007-03-15
申请号：US11445458
申请日：2006-06-02
申请人： Hyo-jong Lee , Ui-hyoung Lee , Hong-jae Shin , Nae-in Lee , Soo-geun Lee
发明人： Hyo-jong Lee , Ui-hyoung Lee , Hong-jae Shin , Nae-in Lee , Soo-geun Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L21/76802 , H01L21/76834 , H01L21/76843
摘要： Methods of fabricating an interconnection line in a semiconductor device and a semiconductor device including such an interconnection line. The method involves forming a lower interconnection line on a semiconductor substrate, forming a mold pattern that defines an opening through which the lower interconnection line is exposed, filling the opening with a conductive material to form a via, removing the mold pattern to make the via remain on the lower interconnection line, forming an interlevel dielectric (ILD) layer that covers the lower interconnection line and the via, patterning the ILD layer, exposing the via, forming a trench that defines a region in which an interconnection line is to be formed, and filling the trench to fabricate a damascene interconnection line connected to the via.
摘要翻译：在半导体器件中制造互连线的方法和包括这种互连线的半导体器件。该方法包括在半导体衬底上形成下部互连线，形成限定下部互连线暴露的开口的模具图案，用导电材料填充开口以形成通孔，去除模具图案以形成通孔保持在下互连线上，形成覆盖下互连线和通孔的层间电介质（ILD）层，图案化ILD层，暴露通孔，形成限定要形成互连线的区域的沟槽，并填充沟槽以制造连接到通孔的镶嵌互连线。

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