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21. 发明申请

US20060059299A1 Apparatus and method for pipelined memory operations 有权
公开(公告)号：US20060059299A1
公开(公告)日：2006-03-16
申请号：US11270251
申请日：2005-11-08
申请人： Richard Barth , Ely Tsern , Mark Horowitz , Donald Stark , Craig Hampel , Frederick Ware , John Dillon , Nancy Dillon
发明人： Richard Barth , Ely Tsern , Mark Horowitz , Donald Stark , Craig Hampel , Frederick Ware , John Dillon , Nancy Dillon
IPC分类号： G06F12/00
CPC分类号： G11C7/1006 , G06F13/1615 , G11C7/10 , G11C7/1039 , G11C8/12 , G11C11/4076
摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

22. 发明申请

US20050237851A1 Asynchronous, high-bandwidth memory component using calibrated timing elements 有权
标题翻译：异步高带宽内存组件使用校准的时序元素
公开(公告)号：US20050237851A1
公开(公告)日：2005-10-27
申请号：US11165797
申请日：2005-06-24
申请人： Frederick Ware , Ely Tsern , Craig Hampel , Donald Stark
发明人： Frederick Ware , Ely Tsern , Craig Hampel , Donald Stark
IPC分类号： G11C7/10 , G11C8/00 , G11C29/02
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
摘要翻译：这里公开了使用内部延迟元件来启用存储器访问流水线的异步存储器件的实施例。在一个实施例中，延迟元件响应于输入负载控制信号，并且参考周期性接收的定时脉冲进行校准。不同数量的延迟元件被配置为产生不同的异步延迟并选择存储器件的顺序流水线元件。

23. 发明申请

US20050235130A1 System for a memory device having a power down mode and method 有权
标题翻译：具有断电模式和方法的存储器件的系统
公开(公告)号：US20050235130A1
公开(公告)日：2005-10-20
申请号：US11151791
申请日：2005-06-14
申请人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
发明人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command. The integrated circuit device generates the value from the information representing the timing parameter pertaining to the random access memory device.
摘要翻译：一种系统，包括存储位置以存储表示随机存取存储器件的定时参数的信息。集成电路装置生成代表在从断电模式退出的随机存取存储装置与随机存取存储装置能够接收指令的时间之间经过的时间段的值。集成电路装置根据表示随机存取存储装置的定时参数的信息生成该值。

24. 发明申请

US20050120161A1 Methods of operation of a memory device and system 有权
标题翻译：存储器件和系统的操作方法
公开(公告)号：US20050120161A1
公开(公告)日：2005-06-02
申请号：US10993046
申请日：2004-11-19
申请人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
发明人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.
摘要翻译：在实施例中提供了存储器件和系统的操作方法。初始化操作在初始化序列期间以第一操作频率进行。然后在第二操作频率下执行存储器存取操作。第二个操作频率高于第一个操作频率。此外，存储器访问操作包括读取操作和写入操作。在实施例中，从串行存在检测装置读取表示第一操作频率和第二操作频率的信息。

25. 发明申请

US20050060487A1 Memory device having a power down exit register 有权
标题翻译：具有断电输出寄存器的存储器件
公开(公告)号：US20050060487A1
公开(公告)日：2005-03-17
申请号：US10944320
申请日：2004-09-17
申请人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
发明人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.
摘要翻译：在一个实施例中，提供了一种包括存储器单元阵列的存储器件以及用于存储表示在从掉电模式恢复之前存储器件准备好接收命令之前经过一段时间的值的寄存器电路。该命令指定对存储单元阵列的访问。延迟锁定环路电路使用外部时钟信号同步数据传输。延迟锁定环路电路在一段时间内重新获得与外部时钟信号的同步。

26. 发明授权

US08278964B2 Method and apparatus for test and characterization of semiconductor components 有权
标题翻译：用于半导体元件测试和表征的方法和装置
公开(公告)号：US08278964B2
公开(公告)日：2012-10-02
申请号：US12554840
申请日：2009-09-04
申请人： Frederick Ware , Scott Best , Timothy Chang , Richard Perego , Ely Tsern , Jeff Mitchell
发明人： Frederick Ware , Scott Best , Timothy Chang , Richard Perego , Ely Tsern , Jeff Mitchell
IPC分类号： G01R31/28
CPC分类号： G11C29/56004 , G01R31/31707 , G06F11/24 , G11C2029/5602
摘要： A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.
摘要翻译：提供了用于测试和表征电路的方法和装置。在一个实施例中，半导体部件的高速接口包括高速测试电路。高速测试电路无需外部高速测试系统进行测试和表征。在一个实施例中，高速测试电路包括测试图形生成电路和各种差分比较器，用于在测试和表征期间将低带宽参考信号与接口信号进行比较。在一个实施例中，包括测试电路的接口可以测试自身或另一接口。在一个实施例中，定时参考信号使彼此测试的两个接口的各个参数解耦，以避免由诸如接收机参数和发射机参数的各个接口电路参数的组合引入的任何错误。测试可以在晶片级，元件级和系统中执行。

27. 发明授权

US07592824B2 Method and apparatus for test and characterization of semiconductor components 有权
标题翻译：用于半导体元件测试和表征的方法和装置
公开(公告)号：US07592824B2
公开(公告)日：2009-09-22
申请号：US10768443
申请日：2004-01-30
申请人： Frederick Ware , Scott Best , Timothy Chang , Richard Perego , Ely Tsern , Jeff Mitchell
发明人： Frederick Ware , Scott Best , Timothy Chang , Richard Perego , Ely Tsern , Jeff Mitchell
IPC分类号： G01R31/02 , G01R31/28
CPC分类号： G11C29/56004 , G01R31/31707 , G06F11/24 , G11C2029/5602
摘要： A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.
摘要翻译：提供了用于测试和表征电路的方法和装置。在一个实施例中，半导体部件的高速接口包括高速测试电路。高速测试电路无需外部高速测试系统进行测试和表征。在一个实施例中，高速测试电路包括测试图形生成电路和各种差分比较器，用于在测试和表征期间将低带宽参考信号与接口信号进行比较。在一个实施例中，包括测试电路的接口可以测试自身或另一接口。在一个实施例中，定时参考信号使彼此测试的两个接口的各个参数解耦，以避免由诸如接收机参数和发射机参数的各个接口电路参数的组合引入的任何错误。测试可以在晶片级，元件级和系统中执行。

28. 发明申请

US20090322370A1 Method And Apparatus For Test And Characterization Of Semiconductor Components 有权
标题翻译：半导体元件测试和表征的方法和装置
公开(公告)号：US20090322370A1
公开(公告)日：2009-12-31
申请号：US12554840
申请日：2009-09-04
申请人： Frederick Ware , Scott Best , Timothy Chang , Richard Perego , Ely Tsern , Jeff Mitchell
发明人： Frederick Ware , Scott Best , Timothy Chang , Richard Perego , Ely Tsern , Jeff Mitchell
IPC分类号： G01R31/02
CPC分类号： G11C29/56004 , G01R31/31707 , G06F11/24 , G11C2029/5602
摘要： A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system.
摘要翻译：提供了用于测试和表征电路的方法和装置。在一个实施例中，半导体部件的高速接口包括高速测试电路。高速测试电路无需外部高速测试系统进行测试和表征。在一个实施例中，高速测试电路包括测试图形生成电路和各种差分比较器，用于在测试和表征期间将低带宽参考信号与接口信号进行比较。在一个实施例中，包括测试电路的接口可以测试自身或另一接口。在一个实施例中，定时参考信号使彼此测试的两个接口的各个参数解耦，以避免由诸如接收机参数和发射机参数的各个接口电路参数的组合引入的任何错误。测试可以在晶片级，元件级和系统中执行。

29. 发明授权

US07685364B2 Memory system topologies including a buffer device and an integrated circuit memory device 有权
标题翻译：存储器系统拓扑，包括缓冲器和集成电路存储器件
公开(公告)号：US07685364B2
公开(公告)日：2010-03-23
申请号：US12424442
申请日：2009-04-15
申请人： Ian Shaeffer , Ely Tsern , Craig Hampel
发明人： Ian Shaeffer , Ely Tsern , Craig Hampel
IPC分类号： G06F12/00
CPC分类号： G11C11/4093 , G06F13/16 , G06F13/4027 , G06F13/4068 , G11C5/025 , G11C5/04 , G11C5/06 , G11C7/1006 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.
摘要翻译：除了其它实施例之外，系统包括集成电路缓冲器件（可耦合到主器件，例如存储器控制器）与多个集成电路存储器件之间的拓扑（数据和/或控制/地址信息）。例如，可以响应于从集成电路缓冲器装置提供的控制/地址信息，在多个集成电路存储器件和集成电路缓冲器件之间使用单独的分段（或点到点链路）信号路径提供数据，所述多个集成电路缓冲器件使用单个飞越（或总线）信号路径。集成电路缓冲器件实现了多个集成电路存储器件的可配置的有效存储器组织。由集成电路缓冲器件表示为存储器控制器的存储器组织可以不同于后面或耦合到集成电路缓冲器件的实际存储器组织。缓冲器设备将期望特定内存组织的内存控制器和实际内存组织之间传输的数据进行分段并合并。

30. 发明申请

US20080080261A1 MEMORY SYSTEM TOPOLOGIES INCLUDING A BUFFER DEVICE AND AN INTEGRATED CIRCUIT MEMORY DEVICE 有权
标题翻译：包括缓冲器器件和集成电路存储器件的存储器系统拓扑
公开(公告)号：US20080080261A1
公开(公告)日：2008-04-03
申请号：US11697572
申请日：2007-04-06
申请人： Ian Shaeffer , Ely Tsern , Craig Hampel
发明人： Ian Shaeffer , Ely Tsern , Craig Hampel
IPC分类号： G11C7/10
CPC分类号： G11C11/4093 , G06F13/16 , G06F13/4027 , G06F13/4068 , G11C5/025 , G11C5/04 , G11C5/06 , G11C7/1006 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.
摘要翻译：除了其它实施例之外，系统包括集成电路缓冲器件（可耦合到主器件，例如存储器控制器）与多个集成电路存储器件之间的拓扑（数据和/或控制/地址信息）。例如，可以响应于从集成电路缓冲器装置提供的控制/地址信息，在多个集成电路存储器件和集成电路缓冲器件之间使用单独的分段（或点到点链路）信号路径提供数据，所述多个集成电路缓冲器件使用单个飞越（或总线）信号路径。集成电路缓冲器件实现了多个集成电路存储器件的可配置的有效存储器组织。由集成电路缓冲器件表示为存储器控制器的存储器组织可以不同于后面或耦合到集成电路缓冲器件的实际存储器组织。缓冲器设备将期望特定内存组织的内存控制器和实际内存组织之间传输的数据进行分段并合并。

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