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21. 发明申请

US20090098727A1 Method of Forming Metal Line of Semiconductor Device 审中-公开
标题翻译：形成半导体器件金属线的方法
公开(公告)号：US20090098727A1
公开(公告)日：2009-04-16
申请号：US12147196
申请日：2008-06-26
申请人： Seung Hee Hong , Cheol Mo Jeong , Eun Soo Kim
发明人： Seung Hee Hong , Cheol Mo Jeong , Eun Soo Kim
IPC分类号： H01L21/768
CPC分类号： H01L21/76846 , H01L21/7684 , H01L21/76882 , H01L23/53214 , H01L2924/0002 , H01L2924/00
摘要： Disclosed herein is a method of forming a metal line of a semiconductor device. According to the method, a contact hole is formed in a second insulating layer over a semiconductor substrate. A first barrier metal layer, including a TiN layer, is formed on a surface of the second insulating layer. The first barrier metal layer is formed such that the TiN layer is formed thinner at a bottom of the contact hole than on sidewalls and a top surface of the second insulating layer. A first metal layer is formed on the first barrier metal layer, including on the contact hole. Thermal treatment is carried to gap-fill the contact hole as the first metal layer is reflown and smooth. A second metal layer is formed on the first metal layer. The second metal layer to form an upper metal line.
摘要翻译：本文公开了形成半导体器件的金属线的方法。根据该方法，在半导体衬底上的第二绝缘层中形成接触孔。在第二绝缘层的表面上形成包括TiN层的第一阻挡金属层。第一阻挡金属层形成为使得TiN层在接触孔的底部比在侧壁和第二绝缘层的顶表面上形成得更薄。第一金属层形成在第一阻挡金属层上，包括在接触孔上。当第一金属层被退光并且光滑时，进行热处理以间隙填充接触孔。第二金属层形成在第一金属层上。第二金属层形成上金属线。

22. 发明授权

US07507628B2 Method of manufacturing a non-volatile memory device 失效
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07507628B2
公开(公告)日：2009-03-24
申请号：US11751015
申请日：2007-05-19
申请人： Seung Hee Hong , Cheol Mo Jeong , Eun Soo Kim
发明人： Seung Hee Hong , Cheol Mo Jeong , Eun Soo Kim
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/42336 , H01L21/763 , H01L27/115 , H01L27/11521
摘要： A method of manufacturing a non-volatile memory device includes forming a trench using the shallow trench isolation (STI) method; forming a first insulating layer on a semiconductor device including the trench; forming a conductive layer on the semiconductor device including the trench; etching the conductive layer to form a conductive layer for a floating gate on an active area and to form a recessed gap-fill conductive layer on an isolation layer; forming a second insulating layer and a third insulating layer on the semiconductor substrate including the gap fill conductive layer and the conductive layer for the floating gate; and etching a portion of the second insulating layer and the third insulating layer to form an isolation structure consisting of the gap fill conductive layer, the second insulating layer and the third insulating layer on the isolation area.
摘要翻译：制造非易失性存储器件的方法包括使用浅沟槽隔离（STI）法形成沟槽; 在包括所述沟槽的半导体器件上形成第一绝缘层; 在包括沟槽的半导体器件上形成导电层; 蚀刻导电层以在有源区上形成用于浮栅的导电层，并在隔离层上形成凹陷间隙填充导电层; 在包括间隙填充导电层和用于浮置栅极的导电层的半导体衬底上形成第二绝缘层和第三绝缘层; 以及蚀刻所述第二绝缘层和所述第三绝缘层的一部分，以形成由隔离区上的间隙填充导电层，第二绝缘层和第三绝缘层组成的隔离结构。

23. 发明申请

US20090065940A1 METAL WIRING OF A SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：半导体器件的金属接线及其形成方法
公开(公告)号：US20090065940A1
公开(公告)日：2009-03-12
申请号：US11951379
申请日：2007-12-06
申请人： Eun Soo Kim , Cheol Mo Jeong , Seung Hee Hong
发明人： Eun Soo Kim , Cheol Mo Jeong , Seung Hee Hong
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/485 , H01L21/76877 , H01L21/76885 , H01L27/11521 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： According to a method of forming a metal wiring of a semiconductor device, a contact plug is formed at height lower than the contact hole, which is formed on an interlayer insulation layer, and then a metal wiring is formed over the contact plug and interlayer insulation layer to completely fill inside of the contact hole, decreasing process difficulty, ensuring reproducibility, and improving electrical property.
摘要翻译：根据形成半导体器件的金属布线的方法，在形成在层间绝缘层上的接触孔的下方形成接触插塞，然后在接触插塞和层间绝缘层上形成金属布线层完全填充接触孔内部，降低工艺难度，确保再现性，并提高电气性能。

24. 发明申请

US20090004814A1 METHOD OF FABRICATING FLASH MEMORY DEVICE 失效
标题翻译：制造闪存存储器件的方法
公开(公告)号：US20090004814A1
公开(公告)日：2009-01-01
申请号：US11964298
申请日：2007-12-26
申请人： Eun Soo Kim , Whee Won Cho , Seung Hee Hong
发明人： Eun Soo Kim , Whee Won Cho , Seung Hee Hong
IPC分类号： H01L21/76
CPC分类号： H01L27/11524 , H01L27/11521
摘要： The invention relates to a method of fabricating a flash memory device. According to the method, select transistors and memory cells are formed on, and junctions are formed in a semiconductor substrate. The semiconductor substrate between a select transistor and an adjacent memory cell are over etched using a hard mask pattern. Accordingly, migration of electrons can be prohibited and program disturbance characteristics can be improved. Further, a void is formed between the memory cells. Accordingly, an interference phenomenon between the memory cells can be reduced and, therefore, the reliability of a flash memory device can be improved.
摘要翻译：本发明涉及一种制造闪速存储器件的方法。根据该方法，在半导体衬底中形成选择晶体管和存储单元，并且形成结。选择晶体管和相邻存储单元之间的半导体衬底使用硬掩模图案过蚀刻。因此，可以禁止电子的迁移，并且可以提高程序干扰特性。此外，在存储单元之间形成空隙。因此，可以减少存储单元之间的干扰现象，因此可以提高闪存器件的可靠性。

25. 发明申请

US20080064204A1 Method of forming a metal line of a semiconductor device 失效
标题翻译：形成半导体器件的金属线的方法
公开(公告)号：US20080064204A1
公开(公告)日：2008-03-13
申请号：US11646925
申请日：2006-12-27
申请人： Eun Soo Kim , Cheol Mo Jeong , Seung Hee Hong
发明人： Eun Soo Kim , Cheol Mo Jeong , Seung Hee Hong
IPC分类号： H01L21/44
CPC分类号： H01L21/76882 , H01L21/76838 , H01L21/76865 , H01L21/76879
摘要： A first conductive layer is formed over a substrate in which contact holes are formed in an interlayer insulating layer. The first conductive layer is melted by an annealing process, thus coating the lower sidewalls of the contact holes and partially filling the contact holes. A second conductive layer is deposited with a method having selectivity with respect to the same material as the first conductive layer, thus fully filling the contact holes. A metal line is formed on the second conductive layer. The contact holes are completely filled with a conductive material and the load of a CMP process can be alleviated. Accordingly, the electrical characteristics of a device can be improved, process reliability can be improved, and process repeatablity can be improved.
摘要翻译：在层间绝缘层中形成有接触孔的基板上形成第一导电层。第一导电层通过退火工艺熔化，从而涂覆接触孔的下侧壁并部分填充接触孔。以与第一导电层相同的材料具有选择性的方法沉积第二导电层，从而完全填充接触孔。金属线形成在第二导电层上。接触孔完全充满导电材料，可以减轻CMP工艺的负荷。因此，可以提高器件的电气特性，提高工艺可靠性，提高加工的可重复性。

26. 发明申请

US20090098722A1 METHOD OF FORMING A SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：形成半导体存储器件的方法
公开(公告)号：US20090098722A1
公开(公告)日：2009-04-16
申请号：US12163956
申请日：2008-06-27
申请人： Jung Geun KIM , Seong Hwan Myung , Eun Soo Kim
发明人： Jung Geun KIM , Seong Hwan Myung , Eun Soo Kim
IPC分类号： H01L21/3205
CPC分类号： H01L21/28273 , H01L29/7881
摘要： A method of forming a semiconductor memory device includes forming a tunnel insulating layer on a semiconductor substrate, and forming a silicon layer, including metal material, on the tunnel insulating layer. Accordingly, an increase in the strain energy of the conductive layer may be prohibited and, therefore, the growth of grains constituting the conductive layer may be prevented. Furthermore, a threshold voltage distribution characteristic and electrical properties of a semiconductor memory device may be improved.
摘要翻译：形成半导体存储器件的方法包括在半导体衬底上形成隧道绝缘层，并在隧道绝缘层上形成包括金属材料的硅层。因此，可以禁止导电层的应变能的增加，因此可以防止构成导电层的晶粒的生长。此外，可以提高半导体存储器件的阈值电压分布特性和电特性。

27. 发明授权

US08692376B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08692376B2
公开(公告)日：2014-04-08
申请号：US13463071
申请日：2012-05-03
申请人： Jung Geun Kim , Whee Won Cho , Eun Soo Kim
发明人： Jung Geun Kim , Whee Won Cho , Eun Soo Kim
IPC分类号： H01L23/48
CPC分类号： H01L21/76883 , H01L21/3215 , H01L21/76825
摘要： A method of manufacturing a semiconductor device includes forming an interlayer dielectric layer, forming trenches by etching the interlayer dielectric layer, forming a copper (Cu) layer to fill the trenches, and implanting at least one of an inert element, a nonmetallic element, and a metallic element onto a surface of the Cu layer.
摘要翻译：一种制造半导体器件的方法包括形成层间电介质层，通过蚀刻层间电介质层形成沟槽，形成铜（Cu）层以填充沟槽，以及注入惰性元素，非金属元素和在Cu层的表面上的金属元素。

28. 发明申请

US20120280397A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120280397A1
公开(公告)日：2012-11-08
申请号：US13463071
申请日：2012-05-03
申请人： Jung Geun KIM , Whee Won Cho , Eun Soo Kim
发明人： Jung Geun KIM , Whee Won Cho , Eun Soo Kim
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76883 , H01L21/3215 , H01L21/76825
摘要： A method of manufacturing a semiconductor device includes forming an interlayer dielectric layer, forming trenches by etching the interlayer dielectric layer, forming a copper (Cu) layer to fill the trenches, and implanting at least one of an inert element, a nonmetallic element, and a metallic element onto a surface of the Cu layer.
摘要翻译：一种制造半导体器件的方法包括形成层间电介质层，通过蚀刻层间电介质层形成沟槽，形成铜（Cu）层以填充沟槽，以及注入惰性元素，非金属元素和在Cu层的表面上的金属元素。

29. 发明授权

US07960231B2 Method of forming a semiconductor memory device 失效
标题翻译：形成半导体存储器件的方法
公开(公告)号：US07960231B2
公开(公告)日：2011-06-14
申请号：US12163956
申请日：2008-06-27
申请人： Jung Geun Kim , Seong Hwan Myung , Eun Soo Kim
发明人： Jung Geun Kim , Seong Hwan Myung , Eun Soo Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L29/7881
摘要： A method of forming a semiconductor memory device includes forming a tunnel insulating layer on a semiconductor substrate, and forming a silicon layer, including metal material, on the tunnel insulating layer. Accordingly, an increase in the strain energy of the conductive layer may be prohibited and, therefore, the growth of grains constituting the conductive layer may be prevented. Furthermore, a threshold voltage distribution characteristic and electrical properties of a semiconductor memory device may be improved.
摘要翻译：形成半导体存储器件的方法包括在半导体衬底上形成隧道绝缘层，并在隧道绝缘层上形成包括金属材料的硅层。因此，可以禁止导电层的应变能的增加，因此可以防止构成导电层的晶粒的生长。此外，可以提高半导体存储器件的阈值电压分布特性和电特性。

30. 发明授权

US07682967B2 Method of forming metal wire in semiconductor device 有权
标题翻译：在半导体器件中形成金属线的方法
公开(公告)号：US07682967B2
公开(公告)日：2010-03-23
申请号：US11801498
申请日：2007-05-10
申请人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
发明人： Eun Soo Kim , Jung Geun Kim , Suk Joong Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/76844 , H01L21/76846 , H01L21/76882 , H01L23/53223 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a metal wire in a semiconductor device is disclosed The method includes the steps of etching an insulating layer formed on a semiconductor substrate to form a dual damascene pattern, forming a barrier metal layer in the dual damascene pattern, forming a metal layer on the barrier metal layer, and filling the dual damascene pattern with a conductive material to form a metal wire.
摘要翻译：公开了一种在半导体器件中形成金属线的方法。该方法包括以下步骤：蚀刻在半导体衬底上形成的绝缘层，以形成双镶嵌图案，在双镶嵌图案中形成阻挡金属层，形成金属层在阻挡金属层上，并用导电材料填充双镶嵌图案以形成金属线。

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