专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20110140218A1 Memory Constructions Comprising Magnetic Materials 有权
标题翻译：包含磁性材料的记忆体构造
公开(公告)号：US20110140218A1
公开(公告)日：2011-06-16
申请号：US13025073
申请日：2011-02-10
申请人： Joel A. Drewes
发明人： Joel A. Drewes
IPC分类号： H01L29/82
CPC分类号： H01L27/222 , G11C11/161 , H01L43/08 , H01L43/12
摘要： The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers are removed from over the block while leaving portions of the first and second layers over the region proximate the block. At least some of the first layer is removed from under the second layer to form a channel over the region proximate the block. A material, such as a soft magnetic material, is provided within the channel. The invention also includes semiconductor constructions.
摘要翻译：本发明包括形成诸如MRAM结构的半导体结构的方法。在半导体衬底上形成块。第一层和第二层形成在块上方，并且在靠近块的衬底的区域上方形成。将第一层和第二层从块上方移除，同时将第一层和第二层的部分留在靠近块的区域上。从第二层下面移除第一层中的至少一些，以在靠近块的区域上形成通道。在通道内提供诸如软磁材料的材料。本发明还包括半导体结构。

22. 发明授权

US07902580B2 Assemblies comprising magnetic elements and magnetic barrier or shielding 有权
标题翻译：组件包括磁性元件和磁屏障或屏蔽
公开(公告)号：US07902580B2
公开(公告)日：2011-03-08
申请号：US12561994
申请日：2009-09-17
申请人： Joel A. Drewes
发明人： Joel A. Drewes
IPC分类号： H01L29/82
CPC分类号： H01L27/222 , G11C11/161 , H01L43/08 , H01L43/12
摘要： The invention includes a method of forming a semiconductor construction, such as an MRAM construction. A block is formed over a semiconductor substrate. First and second layers are formed over the block, and over a region of the substrate proximate the block. The first and second layers are removed from over the block while leaving portions of the first and second layers over the region proximate the block. At least some of the first layer is removed from under the second layer to form a channel over the region proximate the block. A material, such as a soft magnetic material, is provided within the channel. The invention also includes semiconductor constructions.
摘要翻译：本发明包括形成诸如MRAM结构的半导体结构的方法。在半导体衬底上形成块。第一层和第二层形成在块上方，并且在靠近块的衬底的区域上方形成。将第一层和第二层从块上方移除，同时将第一层和第二层的部分留在靠近块的区域上。从第二层下面移除第一层中的至少一些，以在靠近块的区域上形成通道。在通道内提供诸如软磁材料的材料。本发明还包括半导体结构。

23. 发明授权

US07517704B2 MRAM layer having domain wall traps 有权
标题翻译： MRAM层具有域壁陷阱
公开(公告)号：US07517704B2
公开(公告)日：2009-04-14
申请号：US11848893
申请日：2007-08-31
申请人： Joel A. Drewes
发明人： Joel A. Drewes
IPC分类号： H01L41/00
CPC分类号： G11C19/0808 , B82Y25/00 , G11C11/14 , G11C11/15 , G11C2213/77 , H01F10/325 , H01F10/3254 , H01L27/222 , H01L43/08 , H01L43/12
摘要： A common pinned layer is shared by multiple memory cells in an MRAM device. The common pinned layer includes a plurality of domain wall traps that prevent the formation of domain walls within a region of the common pinned layer corresponding to a given memory cell. Therefore, the memory cells can advantageously be formed such that the domain walls, to the extent they exist, fall between (rather than within) the memory cells, thereby improving the performance of the MRAM device.
摘要翻译：常见的固定层由MRAM设备中的多个存储单元共享。共同的被钉扎层包括多个畴壁陷阱，其防止在对应于给定存储单元的公共钉扎层的区域内形成畴壁。因此，可以有利地形成存储器单元，使得它们存在的范围在存储单元之间（而不是在）存储单元之间，从而提高MRAM器件的性能。

24. 发明申请

US20090080240A1 METHOD FOR PRODUCTION OF MRAM ELEMENTS 有权
标题翻译：生产MRAM元件的方法
公开(公告)号：US20090080240A1
公开(公告)日：2009-03-26
申请号：US12323998
申请日：2008-11-26
申请人： Joel A. Drewes
发明人： Joel A. Drewes
IPC分类号： G11C11/00 , G11B5/66
CPC分类号： H01L27/222 , G11C11/161 , H01L43/08 , H01L43/12
摘要： Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the ferromagnetic film. The magnetic dipole aligns with the long axis of each structure. The structures can be formed in a variety of ways. For example, the ferromagnetic film can be applied to a seed layer having a textured surface. Alternatively, the ferromagnetic film can be stressed to generate the textured structure. Chemical mechanical polishing also can be used to generated the structures.
摘要翻译：磁阻随机存取存储元件包括由在铁磁膜中形成的细长结构提供的具有单轴各向异性的铁磁层。磁偶极子与每个结构的长轴对齐。可以以各种方式形成结构。例如，铁磁膜可以施加到具有纹理表面的种子层。或者，铁磁膜可以被应力以产生纹理结构。化学机械抛光也可用于生成结构。

25. 发明授权

US07402833B2 Multilayer dielectric tunnel barrier used in magnetic tunnel junction devices, and its method of fabrication 有权
标题翻译：用于磁隧道结装置的多层电介质隧道势垒及其制造方法
公开(公告)号：US07402833B2
公开(公告)日：2008-07-22
申请号：US11106509
申请日：2005-04-15
申请人： Joel A. Drewes
发明人： Joel A. Drewes
IPC分类号： H01L29/06 , H01L29/08 , H01L39/00
CPC分类号： C23C16/303 , B82Y25/00 , C23C16/403 , C23C16/45529 , H01F10/3254 , H01F41/22 , H01F41/32 , H01L21/02178 , H01L21/0228 , H01L21/3162 , H01L21/31683 , H01L43/12
摘要： A multilayer dielectric tunnel barrier structure and a method for its formation which may be used in non-volatile magnetic memory elements comprises an ALD deposited first nitride junction layer formed from one or more nitride monolayers i.e., AlN, an ALD deposited intermediate oxide junction layer formed from one or more oxide monolayers i.e., AlxOy, disposed on the first nitride junction layer, and an ALD deposited second nitride junction layer formed from one or more nitride monolayers i.e., AlN, disposed on top of the intermediate oxide junction layer. The multilayer tunnel barrier structure is formed by using atomic layer deposition techniques to provide improved tunneling characteristics while also providing anatomically smooth barrier interfaces.
摘要翻译：可用于非易失性磁存储元件的多层介质隧道势垒结构及其形成方法包括由一个或多个氮化物单层形成的ALD沉积的第一氮化物结层，即AlN，形成的ALD沉积的中间氧化物结层设置在第一氮化物结层上的一个或多个氧化物单层，即Al x O y O y，以及由一个或多个氮化物单层形成的ALD沉积的第二氮化物结层即AlN，设置在中间氧化物结层的顶部。通过使用原子层沉积技术来形成多层隧道势垒结构，以提供改进的隧道特性，同时还提供解剖平滑的屏障界面。

26. 发明授权

US07112454B2 System and method for reducing shorting in memory cells 有权
标题翻译：用于减少存储器单元短路的系统和方法
公开(公告)号：US07112454B2
公开(公告)日：2006-09-26
申请号：US10684967
申请日：2003-10-14
申请人： Joel A. Drewes , James G. Deak
发明人： Joel A. Drewes , James G. Deak
IPC分类号： H01L21/70 , G11C11/15
CPC分类号： H01L27/222 , H01L43/08 , H01L43/12
摘要： An MRAM device includes an array of magnetic memory cells having an upper conductive layer and a lower conductive layer separated by a barrier layer. To reduce the likelihood of electrical shorting across the barrier layers of the memory cells, spacers can be formed around the upper conductive layer and, after the layers of the magnetic memory cells have been etched, the memory cells can be oxidized to transform any conductive particles that are deposited along the sidewalls of the memory cells as byproducts of the etching process into nonconductive particles. Alternatively, the lower conductive layer can be repeatedly subjected to partial oxidation and partial etching steps such that only nonconductive particles can be thrown up along the sidewalls of the memory cells as byproducts of the etching process.
摘要翻译： MRAM器件包括具有由阻挡层隔开的上导电层和下导电层的磁存储单元的阵列。为了减少跨越存储器单元的阻挡层的电短路的可能性，可以在上导电层周围形成间隔物，并且在已经蚀刻了磁存储单元的层之后，可以将存储单元氧化以转换任何导电颗粒沿着存储器单元的侧壁沉积作为蚀刻工艺的副产物而形成非导电颗粒。或者，下导电层可以重复进行部分氧化和部分蚀刻步骤，使得只有非导电颗粒可以作为蚀刻工艺的副产物沿着存储器单元的侧壁被抛出。

27. 发明授权

US06902940B2 Method for manufacture of MRAM memory elements 有权
标题翻译：制造MRAM存储元件的方法
公开(公告)号：US06902940B2
公开(公告)日：2005-06-07
申请号：US10644882
申请日：2003-08-21
申请人： Joel A. Drewes
发明人： Joel A. Drewes
IPC分类号： G11C7/00 , H01L21/00 , H01L27/22 , H01L31/119 , H01L43/08
CPC分类号： H01L27/222 , H01L43/08
摘要： A magnetic memory element has reduced demagnetization coupling between a pinned layer and a free layer. The element includes a pinned ferromagnetic layer and a free ferromagnetic layer which are separated by a barrier layer. The pinned layer is pinned by an antiferromagnetic layer. An offset ferromagnetic layer is provided on a side of the antiferromagnetic layer opposite the pinned ferromagnetic layer to reduce demagnetization coupling between the free ferromagnetic layer and the pinned ferromagnetic layer.
摘要翻译：磁存储元件减少了被钉扎层和自由层之间的去磁耦合。元件包括被阻挡层分隔的钉扎铁磁层和自由铁磁层。被钉扎层被反铁磁层固定。偏转铁磁层设置在与被钉扎的铁磁层相对的反铁磁层的一侧上，以减少游离铁磁层与被钉扎的铁磁层之间的去磁耦合。

28. 发明授权

US06881993B2 Device having reduced diffusion through ferromagnetic materials 有权
标题翻译：装置通过铁磁材料减少扩散
公开(公告)号：US06881993B2
公开(公告)日：2005-04-19
申请号：US10229139
申请日：2002-08-28
申请人： Joel A. Drewes , Terry Gafron
发明人： Joel A. Drewes , Terry Gafron
IPC分类号： H01F10/32 , H01F41/30 , H01L31/119
CPC分类号： B82Y25/00 , B82Y40/00 , H01F10/3254 , H01F41/302
摘要： A method and apparatus are disclosed for inhibiting diffusion of mobile atoms from an antiferromagnetic layer toward a tunnel oxide layer and through a ferromagnetic layer which is pinned by the antiferromagnetic layer. Diffusion of the mobile atoms is inhibited by an oxide layer provided between the anti-ferromagnetic layer and the ferromagnetic layer. Alternatively, the ferromagnetic layer can have boron atoms located on or in the layer to fill interstices.
摘要翻译：公开了一种用于抑制移动原子从反铁磁层向隧道氧化物层扩散并通过由反铁磁层固定的铁磁层的扩散的方法和装置。通过设置在反铁磁层和铁磁层之间的氧化物层来抑制移动原子的扩散。或者，铁磁层可以具有位于层中或层中的硼原子以填充间隙。

29. 发明授权

US06870714B2 Oxide buffer layer for improved magnetic tunnel junctions 有权
标题翻译：用于改善磁隧道结的氧化物缓冲层
公开(公告)号：US06870714B2
公开(公告)日：2005-03-22
申请号：US10385858
申请日：2003-03-12
申请人： Joel A. Drewes
发明人： Joel A. Drewes
IPC分类号： B32B19/00 , G11B5/127 , H01L27/22 , H01L43/08 , H01L43/12
CPC分类号： H01L43/08 , H01L27/222 , H01L43/12 , Y10T428/1114 , Y10T428/1193 , Y10T428/12465 , Y10T428/12611 , Y10T428/12931 , Y10T428/265 , Y10T428/32
摘要： A metal manganese oxide buffer layer is used to seed a barrier layer in a magnetic tunnel junction memory element having pinned and free magnetic layers. An alumina tunnel barrier layer is formed on the oxidized metal manganese layer with the barrier layer and oxidized metal manganese layer being between the pinned or free ferromagnetic layers.
摘要翻译：使用金属锰氧化物缓冲层来将具有固定和自由磁性层的磁性隧道结存储元件中的阻挡层接种。在具有阻挡层的氧化金属锰层上形成氧化铝隧道势垒层，在被钉扎或游离的铁磁层之间形成氧化金属锰层。

30. 发明授权

US06743641B2 Method of improving surface planarity prior to MRAM bit material deposition 有权
标题翻译：在MRAM钻头材料沉积之前提高表面平面度的方法
公开(公告)号：US06743641B2
公开(公告)日：2004-06-01
申请号：US10022721
申请日：2001-12-20
申请人： Donald L. Yates , Joel A. Drewes
发明人： Donald L. Yates , Joel A. Drewes
IPC分类号： H01L2100
CPC分类号： H01L27/222 , G11C11/15 , H01L21/7684
摘要： The present invention provides a method of fabricating a portion of a memory cell, the method comprising providing a first conductor in a trench which is provided in an insulating layer and flattening an upper surface of the insulating layer and the first conductor, forming a material layer over the flattened upper surface of the insulating layer and the first conductor and flattening an upper portion of the material layer while leaving intact a lower portion of the material layer over the insulating layer and the first conductor.
摘要翻译：本发明提供了一种制造存储单元的一部分的方法，该方法包括提供一沟槽中的第一导体，其设置在绝缘层中并使绝缘层和第一导体的上表面平坦化，形成材料层在绝缘层和第一导体的平坦的上表面上方，并且使材料层的上部平坦化，同时在绝缘层和第一导体上完整地保留材料层的下部。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式