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21. 发明申请

US20080204154A1 Method and Enhanced Phase Locked Loop Circuits for Implementing Effective Testing 失效
标题翻译：用于实现有效测试的方法和增强型锁相环电路
公开(公告)号：US20080204154A1
公开(公告)日：2008-08-28
申请号：US11679323
申请日：2007-02-27
申请人： Michael David Cesky , James David Strom
发明人： Michael David Cesky , James David Strom
IPC分类号： H03J7/04
CPC分类号： H03L7/1974 , G06F1/08
摘要： A method and enhanced phase-locked loop (PLL) circuit enable effective testing of the PLL. A phase frequency detector generates a differential signal, receiving a reference signal and a feedback signal of an output signal of the PLL circuit. A charge pump is coupled to the phase frequency detector receiving the differential signal. The charge pump applies either negative or positive charge pulses to a low-pass filter, which generates a tuning voltage input applied to a voltage controlled oscillator. A first divider is coupled to the voltage controlled oscillator receives and divides down the VCO output signal, providing the output signal of the PLL circuit. A second divider receives the output signal of the PLL circuit and provides the feedback signal to the phase frequency detector. The output signal of PLL circuit is applied to a clock distribution.
摘要翻译：一种方法和增强型锁相环（PLL）电路能够有效地测试PLL。相位频率检测器产生差分信号，接收PLL电路的输出信号的参考信号和反馈信号。电荷泵耦合到接收差分信号的相位频率检测器。电荷泵将负电荷或正电荷脉冲施加到低通滤波器，产生施加到压控振荡器的调谐电压输入。第一分频器耦合到压控振荡器接收并分频VCO输出信号，提供PLL电路的输出信号。第二分频器接收PLL电路的输出信号，并将反馈信号提供给相位频率检测器。 PLL电路的输出信号应用于时钟分配。

22. 发明申请

US20080116947A1 Method and Apparatus for Distributing Charge Pump Current and Voltage for PLL Circuits 审中-公开
标题翻译：用于分配PLL电路的电荷泵电流和电压的方法和装置
公开(公告)号：US20080116947A1
公开(公告)日：2008-05-22
申请号：US11561431
申请日：2006-11-20
申请人： Katherine Ellen Lobb , James David Strom
发明人： Katherine Ellen Lobb , James David Strom
IPC分类号： H03L7/08
CPC分类号： H03L7/0891 , H03L7/18
摘要： A method and apparatus for distributing charge pump current and voltage for phase-locked loop circuits includes a charge pump implemented with a plurality of charge pump stages, each providing substantially equal charge pump current. Each stage includes a respective associated buffer for receiving an incoming increment (INC) signal and an incoming decrement (DEC) signal and providing an output time delayed INC signal and an output time delayed DEC. A chain of the buffers is provided to pass the time delayed INC signals and the time delayed DEC signals to the respective charge pump stages. Each of the charge pump stages includes an enable input arranged for independently enabling each respective charge pump stage.
摘要翻译：用于分配用于锁相环电路的电荷泵电流和电压的方法和装置包括用多个电荷泵级实现的电荷泵，每个电荷泵提供基本相等的电荷泵电流。每个级包括用于接收输入增量（INC）信号和进入递减（DEC）信号并提供输出时间延迟INC信号和输出时间延迟DEC的各自相关联的缓冲器。提供缓冲器链以将时间延迟的INC信号和时间延迟的DEC信号传递到各个电荷泵级。每个电荷泵级包括使能输入，其被布置用于独立地使能各个电荷泵级。

23. 发明授权

US07118274B2 Method and reference circuit for bias current switching for implementing an integrated temperature sensor 失效
标题翻译：用于实现集成温度传感器的偏置电流开关的方法和参考电路
公开(公告)号：US07118274B2
公开(公告)日：2006-10-10
申请号：US10849580
申请日：2004-05-20
申请人： Nghia Van Phan , Patrick Lee Rosno , James David Strom
发明人： Nghia Van Phan , Patrick Lee Rosno , James David Strom
IPC分类号： G01K7/01 , G01K7/14 , G05F3/24 , G05F3/26
CPC分类号： G01K7/01
摘要： A method and a reference circuit for bias current switching are provided for implementing an integrated temperature sensor. A first bias current is generated and constantly applied to a thermal sensing diode. A second bias current is provided to the thermal sensing diode by selectively switching a multiplied current from a current multiplier to the thermal sensing diode or to a load diode. The reference circuit includes a reference current source coupled to current mirror. The current mirror provides a first bias current to a thermal sensing diode. The current mirror is coupled to a current multiplier that provides a multiplied current. A second bias current to the thermal sensing diode includes the first bias current and the multiplied current from the current multiplier. The second bias current to the thermal sensing diode is provided by selectively switching the multiplied current between the thermal sensing diode and a dummy load diode.
摘要翻译：提供了用于实现集成温度传感器的偏置电流切换的方法和参考电路。产生第一偏置电流并且恒定地施加到热感测二极管。通过选择性地将乘法电流从电流乘法器切换到热感测二极管或负载二极管，来向热感测二极管提供第二偏置电流。参考电路包括耦合到电流镜的参考电流源。电流镜向热敏二极管提供第一偏置电流。电流镜耦合到提供倍增电流的电流倍增器。到热敏二极管的第二偏置电流包括第一偏置电流和来自当前乘法器的相乘电流。通过选择性地切换热感测二极管和虚拟负载二极管之间的倍增电流来提供到热敏二极管的第二偏置电流。

24. 发明授权

US06724256B1 Receiver with delay insensitive to input amplitude and slew rate 失效
标题翻译：接收器对输入幅度和转换速率不敏感
公开(公告)号：US06724256B1
公开(公告)日：2004-04-20
申请号：US10289604
申请日：2002-11-07
申请人： James David Strom , Patrick Lee Rosno
发明人： James David Strom , Patrick Lee Rosno
IPC分类号： H03F345
CPC分类号： H03F3/45278 , H03F3/45085 , H03F2203/45646 , H03F2203/45652 , H03F2203/45722
摘要： A receiver is provided with delay generally insensitive to input amplitude and slew rate. The receiver includes a first differential transistor pair having a common emitter connection. A differential input is applied to a respective base of the differential transistor pair. A pair of load transistors is connected to the respective collector of the differential transistor pair. A respective resistance is coupled to a base of the load transistors for providing a delay independent of the differential input; and a pair of bias transistors is coupled to the respective collector of the differential transistor pair for biasing the load transistors.
摘要翻译：接收机具有对输入幅度和转换速率通常不敏感的延迟。接收器包括具有共同发射极连接的第一差分晶体管对。差分输入被施加到差分晶体管对的相应基极。一对负载晶体管连接到差分晶体管对的各个集电极。相应的电阻耦合到负载晶体管的基极，用于提供独立于差分输入的延迟; 并且一对偏置晶体管耦合到差分晶体管对的相应集电极以偏置负载晶体管。

25. 发明授权

US08686782B2 Structure for a frequency adaptive level shifter circuit 有权
标题翻译：频率自适应电平转换电路的结构
公开(公告)号：US08686782B2
公开(公告)日：2014-04-01
申请号：US12956343
申请日：2010-11-30
申请人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
发明人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
IPC分类号： H03L5/00
CPC分类号： H03K4/94 , H03L9/00
摘要： The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.
摘要翻译：本发明提供了一种用于频率自适应电平移位器电路的装置和方法。频率自适应电平移位器电路包括第一反相器，耦合到第一反相器的输出的第二反相器，耦合到第二反相器的输出的电容器和耦合到电容器的输出的电阻器。频率自适应电平移位器电路还包括耦合到电阻器的输出的晶体管，其中晶体管具有连接到参考电压的栅极，耦合到电容器的输出的第三反相器和耦合到第三反相器和晶体管并输出信号。

26. 发明申请

US20120187987A1 STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT 有权
标题翻译：频率自适应电平变换电路的结构
公开(公告)号：US20120187987A1
公开(公告)日：2012-07-26
申请号：US13431599
申请日：2012-03-27
申请人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
发明人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
IPC分类号： H03L7/08 , H03L5/00
CPC分类号： H03K4/94 , H03L9/00
摘要： The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.
摘要翻译：本发明提供了一种用于频率自适应电平移位器电路的装置和方法。频率自适应电平移位器电路包括第一反相器，耦合到第一反相器的输出的第二反相器，耦合到第二反相器的输出的电容器和耦合到电容器的输出的电阻器。频率自适应电平移位器电路还包括耦合到电阻器的输出的晶体管，其中晶体管具有连接到参考电压的栅极，耦合到电容器的输出的第三反相器和耦合到第三反相器和晶体管并输出信号。

27. 发明申请

US20120133413A1 DESIGN STRUCTURE FOR A FREQUENCY ADAPTIVE LEVEL SHIFTER CIRCUIT 有权
标题翻译：一种频率自适应电平变换电路的设计结构
公开(公告)号：US20120133413A1
公开(公告)日：2012-05-31
申请号：US12956343
申请日：2010-11-30
申请人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
发明人： Joel Thomas Ficke , David Michael Friend , Grant Paul Kesselring , James David Strom , Jianguo Yao
IPC分类号： H03L5/00
CPC分类号： H03K4/94 , H03L9/00
摘要： The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.
摘要翻译：本发明提供了一种用于频率自适应电平移位器电路的装置和方法。频率自适应电平移位器电路包括第一反相器，耦合到第一反相器的输出的第二反相器，耦合到第二反相器的输出的电容器和耦合到电容器的输出的电阻器。频率自适应电平移位器电路还包括耦合到电阻器的输出的晶体管，其中晶体管具有连接到参考电压的栅极，耦合到电容器的输出的第三反相器和耦合到第三反相器和晶体管并输出信号。

28. 发明申请

US20080116959A1 Method and Apparatus for Distributing Charge Pump Current and Voltage for PLL Circuits 审中-公开
标题翻译：用于分配PLL电路的电荷泵电流和电压的方法和装置
公开(公告)号：US20080116959A1
公开(公告)日：2008-05-22
申请号：US11872356
申请日：2007-10-15
申请人： Katherine Ellen Hirsch , James David Strom
发明人： Katherine Ellen Hirsch , James David Strom
IPC分类号： G05F1/10
CPC分类号： H03L7/0891 , H03L7/18
摘要： A method and apparatus for distributing charge pump current and voltage for phase-locked loop circuits, and a design structure on which the subject circuit resides are provided. A charge pump implemented with a plurality of charge pump stages, each providing substantially equal charge pump current. Each stage includes a respective associated buffer for receiving an incoming increment (INC) signal and an incoming decrement (DEC) signal and providing an output time delayed INC signal and an output time delayed DEC. A chain of the buffers is provided to pass the time delayed INC signals and the time delayed DEC signals to the respective charge pump stages. Each of the charge pump stages includes an enable input arranged for independently enabling each respective charge pump stage.
摘要翻译：一种用于分配锁相环电路的电荷泵电流和电压的方法和装置，以及设置有被摄体电路的设计结构。一种电荷泵，其具有多个电荷泵级，各自提供基本上相等的电荷泵电流。每个级包括用于接收输入增量（INC）信号和进入递减（DEC）信号并提供输出时间延迟INC信号和输出时间延迟DEC的各自相关联的缓冲器。提供缓冲器链以将时间延迟的INC信号和时间延迟的DEC信号传递到各个电荷泵级。每个电荷泵级包括使能输入，其被布置用于独立地使能各个电荷泵级。

29. 发明授权

US06693465B1 Open input sense for differential receiver 失效
标题翻译：差分接收器的开路输入检测
公开(公告)号：US06693465B1
公开(公告)日：2004-02-17
申请号：US10345558
申请日：2003-01-16
申请人： Patrick Lee Rosno , James David Strom
发明人： Patrick Lee Rosno , James David Strom
IPC分类号： H03K522
CPC分类号： H03K5/2481 , H04L25/08
摘要： Circuitry is disclosed for detection of open inputs on an enhanced differential receiver. A pulldown terminator is coupled to the inputs of the enhanced differential receiver. If the differential inputs are not actively driven, the voltage on both differential inputs will be pulled to a predetermined voltage. When the voltage on the differential inputs reach a reference voltage, an active device detects that the reference voltage has been reached, and produces a predetermined logic value on an output of the enhanced differential receiver. The enhanced differential receiver is not subject to oscillation when not actively driven. Delay through the enhanced differential receiver is not substantially greater than delay through a conventional differential receiver consisting of only a differential amplifier.
摘要翻译：公开了用于检测增强型差分接收器上的开放输入的电路。下拉终端器耦合到增强型差分接收器的输入端。如果差分输入未被主动驱动，则两个差分输入端的电压将被拉至预定的电压。当差分输入上的电压达到参考电压时，有源器件检测到已经达到参考电压，并且在增强差分接收器的输出上产生预定的逻辑值。增强型差分接收器不主动驱动时不会发生振荡。通过增强型差分接收器的延迟通过仅由差分放大器组成的常规差分接收器的延迟实质上不大。

30. 发明授权

US06535986B1 Optimizing performance of a clocked system by adjusting clock control settings and clock frequency 失效
标题翻译：通过调整时钟控制设置和时钟频率来优化时钟系统的性能
公开(公告)号：US06535986B1
公开(公告)日：2003-03-18
申请号：US09524878
申请日：2000-03-14
申请人： Patrick Lee Rosno , James David Strom
发明人： Patrick Lee Rosno , James David Strom
IPC分类号： G06F108
CPC分类号： G06F1/324 , G06F1/3203 , Y02D10/126
摘要： A method of adjusting the operating or timing margin of a clocked system, such as a digital computer or a memory controller, is disclosed. The method may be automated to occur upon every initial program load or can be manually adjusted for changes in frequency, operating voltages, or applications in which the timing margin is not so critical. An initial or default frequency of the clock is set. Clock control settings, such as duty cycle, VCO range and gain, etc, are also initialized and set as some default. Test, such as ABIST, LBIST or other functional tests, are performed on the clocked system and the clock frequency is incrementally increased until the tests fail. Upon failure of the tests, one or more clock control settings are adjusted and the tests are run again at the failing frequency. If the tests successfully complete, indicating no errors, the clock frequency is incremented again until the test fail. Again, the clock control settings are adjusted and the tests are repeated at increasing frequency until failure of the tests or until a desired timing margin is reached.
摘要翻译：公开了一种调节计时系统（如数字计算机或存储器控制器）的操作或定时裕度的方法。该方法可以在每个初始程序加载时自动发生，或者可以针对频率，操作电压或其中定时裕度不那么关键的应用进行手动调整。设置时钟的初始或默认频率。诸如占空比，VCO范围和增益等的时钟控制设置也被初始化并设置为一些默认值。在时钟系统上执行诸如ABIST，LBIST或其他功能测试的测试，并且时钟频率逐渐增加，直到测试失败。测试失败后，调整一个或多个时钟控制设置，并在故障频率下再次运行测试。如果测试成功完成，表明没有错误，则时钟频率再次递增，直到测试失败。再次，时钟控制设置被调整，测试以增加的频率重复，直到测试失败或直到达到期望的时序余量。

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