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21. 发明申请

US20070198868A1 Memory System Having Delayed Write Timing 有权
标题翻译：具有延迟写入时序的存储器系统
公开(公告)号：US20070198868A1
公开(公告)日：2007-08-23
申请号：US11692162
申请日：2007-03-27
申请人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarro , David Nguyen
发明人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarro , David Nguyen
IPC分类号： H04L7/033
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： A memory system has first, second and third interconnects and an integrated circuit memory device coupled to the interconnects. The second interconnect conveys a write command and a read command. The third interconnect conveys write data and read data. The integrated circuit memory device includes a pin coupled to the first interconnect to receive a clock signal. The memory device also includes a first plurality of pins coupled to the second interconnect to receive the write command and read command, and a second plurality of pins coupled to the third interconnect to receive write data and to assert read data. Control information is applied to initiate the write operation after a first predetermined delay time transpires from when the write command is received. During a clock cycle of the clock signal, two bits of read data are conveyed by each pin of the second plurality of pins.
摘要翻译：存储器系统具有第一，第二和第三互连以及耦合到互连的集成电路存储器件。第二个互连传送写入命令和读取命令。第三个互连传送写入数据和读取数据。集成电路存储器件包括耦合到第一互连的引脚以接收时钟信号。存储器件还包括耦合到第二互连以接收写入命令和读取命令的第一多个引脚，以及耦合到第三互连以接收写入数据和断言读取数据的第二多个引脚。应用控制信息以在从接收到写入命令之后发生第一预定延迟时间之后启动写入操作。在时钟信号的时钟周期期间，第二多个引脚的每个引脚传送两位读取数据。

22. 发明申请

US20070242532A1 Integrated Circuit Memory Device Having Delayed Write Timing Based on Read Response Time 有权
标题翻译：具有基于读响应时间的延迟写时序的集成电路存储器件
公开(公告)号：US20070242532A1
公开(公告)日：2007-10-18
申请号：US11692159
申请日：2007-03-27
申请人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarro , David Nguyen
发明人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarro , David Nguyen
IPC分类号： G11C7/10 , G06F13/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermined delay time transpires following receipt of the write command, the control information initiating the write operation in the memory device. A second set of pins output the read data after a first delay time transpires from when the read command is received. Each pin of the second set of pins outputs two bits of read data during a clock cycle of the clock signal. The second set of pins also receive write data after a second delay time has transpired from when the write command is received. The second delay time is based on the first delay time.
摘要翻译：集成电路存储器件包括第一组引脚和存储器核。第一组引脚使用时钟信号接收写入命令和读取命令。控制信息在接收到写入命令之后经过预定的延迟时间之后响应写入命令被发出，控制信息在存储器件中启动写入操作。第二组引脚在从接收到读命令之后发生第一延迟时间后输出读数据。第二组引脚的每个引脚在时钟信号的时钟周期期间输出两位读取数据。第二组引脚还在接收到写入命令之后延迟了第二个延迟时间之后也接收到写入数据。第二延迟时间基于第一延迟时间。

23. 发明申请

US20070159912A1 Integrated Circuit Memory Device with Delayed Write Command Processing 有权
标题翻译：具有延迟写命令处理的集成电路存储器件
公开(公告)号：US20070159912A1
公开(公告)日：2007-07-12
申请号：US11681384
申请日：2007-03-02
申请人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarro , David Nguyen
发明人： Richard Barth , Frederick Ware , Donald Stark , Craig Hampel , Paul Davis , Abhijit Abhyankar , James Gasbarro , David Nguyen
IPC分类号： G06F13/28 , G11C8/00 , G11C7/00 , G06F12/00
CPC分类号： G11C7/22 , G11C7/1006 , G11C7/12 , G11C8/12 , G11C8/18 , G11C11/406 , G11C11/40611 , G11C11/4076 , G11C11/4093 , G11C11/4096 , G11C2207/2218
摘要： An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to receive a sense command followed by a write command. The sense command specifies the sensing of a row of memory cells identified by the row address, and the write command specifies that the memory device receive write data and store the write data at a column location identified by the column address. The write command is posted internally to the memory device after a first delay has transpired from when the write command is received at the second set of pins.
摘要翻译：具有延迟写入命令处理的集成电路存储器件包括耦合到存储器核心的第一组引脚，第一组引脚以接收列地址的行地址。耦合到存储器核心的第二组引脚用于接收感测命令，后接写入命令。感测命令指定感测由行地址识别的一行存储器单元，并且写入命令指定存储器件接收写入数据并将写入数据存储在由列地址标识的列位置处。在从第二组引脚接收到写命令之后第一个延迟发生之后，写入命令在内部发布到存储器件中。

24. 发明授权

US07685364B2 Memory system topologies including a buffer device and an integrated circuit memory device 有权
标题翻译：存储器系统拓扑，包括缓冲器和集成电路存储器件
公开(公告)号：US07685364B2
公开(公告)日：2010-03-23
申请号：US12424442
申请日：2009-04-15
申请人： Ian Shaeffer , Ely Tsern , Craig Hampel
发明人： Ian Shaeffer , Ely Tsern , Craig Hampel
IPC分类号： G06F12/00
CPC分类号： G11C11/4093 , G06F13/16 , G06F13/4027 , G06F13/4068 , G11C5/025 , G11C5/04 , G11C5/06 , G11C7/1006 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.
摘要翻译：除了其它实施例之外，系统包括集成电路缓冲器件（可耦合到主器件，例如存储器控制器）与多个集成电路存储器件之间的拓扑（数据和/或控制/地址信息）。例如，可以响应于从集成电路缓冲器装置提供的控制/地址信息，在多个集成电路存储器件和集成电路缓冲器件之间使用单独的分段（或点到点链路）信号路径提供数据，所述多个集成电路缓冲器件使用单个飞越（或总线）信号路径。集成电路缓冲器件实现了多个集成电路存储器件的可配置的有效存储器组织。由集成电路缓冲器件表示为存储器控制器的存储器组织可以不同于后面或耦合到集成电路缓冲器件的实际存储器组织。缓冲器设备将期望特定内存组织的内存控制器和实际内存组织之间传输的数据进行分段并合并。

25. 发明申请

US20080080261A1 MEMORY SYSTEM TOPOLOGIES INCLUDING A BUFFER DEVICE AND AN INTEGRATED CIRCUIT MEMORY DEVICE 有权
标题翻译：包括缓冲器器件和集成电路存储器件的存储器系统拓扑
公开(公告)号：US20080080261A1
公开(公告)日：2008-04-03
申请号：US11697572
申请日：2007-04-06
申请人： Ian Shaeffer , Ely Tsern , Craig Hampel
发明人： Ian Shaeffer , Ely Tsern , Craig Hampel
IPC分类号： G11C7/10
CPC分类号： G11C11/4093 , G06F13/16 , G06F13/4027 , G06F13/4068 , G11C5/025 , G11C5/04 , G11C5/06 , G11C7/1006 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.
摘要翻译：除了其它实施例之外，系统包括集成电路缓冲器件（可耦合到主器件，例如存储器控制器）与多个集成电路存储器件之间的拓扑（数据和/或控制/地址信息）。例如，可以响应于从集成电路缓冲器装置提供的控制/地址信息，在多个集成电路存储器件和集成电路缓冲器件之间使用单独的分段（或点到点链路）信号路径提供数据，所述多个集成电路缓冲器件使用单个飞越（或总线）信号路径。集成电路缓冲器件实现了多个集成电路存储器件的可配置的有效存储器组织。由集成电路缓冲器件表示为存储器控制器的存储器组织可以不同于后面或耦合到集成电路缓冲器件的实际存储器组织。缓冲器设备将期望特定内存组织的内存控制器和实际内存组织之间传输的数据进行分段并合并。

26. 发明申请

US20070028060A1 Low power memory device 有权
标题翻译：低功耗存储设备
公开(公告)号：US20070028060A1
公开(公告)日：2007-02-01
申请号：US11194812
申请日：2005-08-01
申请人： Frederick Ware , Ely Tsern , Craig Hampel
发明人： Frederick Ware , Ely Tsern , Craig Hampel
IPC分类号： G06F13/00
CPC分类号： G11C7/1006 , G11C5/14 , G11C7/1039 , G11C7/1045 , G11C7/1051 , G11C7/1096 , G11C7/22 , G11C7/222 , G11C8/08 , G11C8/12 , G11C11/4063 , G11C11/4076 , G11C11/4085 , G11C2207/2227
摘要： In a memory device having a memory core and a signal interface, receiving a command that specifies at least a portion of a memory access. During the memory access, transferring data between the memory core and the signaling interface, and transferring the data between the signaling interface and an external signal path, and prior to transferring the data between the signaling interface and the external signal path, receiving enable information to selectively enable at least a first memory resource and a second memory resource, wherein each of the first memory resource and the second memory resource performs a control function associated with the memory access.
摘要翻译：在具有存储器核心和信号接口的存储器件中，接收指定存储器访问的至少一部分的命令。在存储器访问期间，在存储器核心和信令接口之间传送数据，并且在信令接口和外部信号路径之间传送数据，并且在信令接口和外部信号路径之间传送数据之前，接收使能信息选择性地启用至少第一存储器资源和第二存储器资源，其中第一存储器资源和第二存储器资源中的每一个执行与存储器访问相关联的控制功能。

27. 发明申请

US20050142950A1 Multiple channel modules and bus systems using same 失效
标题翻译：多通道模块和使用相同的总线系统
公开(公告)号：US20050142950A1
公开(公告)日：2005-06-30
申请号：US11054955
申请日：2005-02-11
申请人： Belgacem Haba , Richard Perego , David Nguyen , Billy Garrett , Ely Tsern , Craig Hampel , Wai-Yeung Yip
发明人： Belgacem Haba , Richard Perego , David Nguyen , Billy Garrett , Ely Tsern , Craig Hampel , Wai-Yeung Yip
IPC分类号： G06F13/40 , G11C5/00 , H05K1/02 , H05K1/11 , H05K1/14 , H05K7/06 , H05K7/14 , H01R24/00
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
摘要翻译：公开了可用于实现具有1至N个信道的模块的各种模块结构。总线系统可以通过这种模块的互连形成。

28. 发明授权

US08539152B2 Memory system topologies including a buffer device and an integrated circuit memory device 有权
公开(公告)号：US08539152B2
公开(公告)日：2013-09-17
申请号：US13149682
申请日：2011-05-31
申请人： Ian Shaeffer , Ely Tsern , Craig Hampel
发明人： Ian Shaeffer , Ely Tsern , Craig Hampel
IPC分类号： G06F12/00
CPC分类号： G11C11/4093 , G06F13/16 , G06F13/4027 , G06F13/4068 , G11C5/025 , G11C5/04 , G11C5/06 , G11C7/1006 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

29. 发明申请

US20070247935A1 Clocked Memory System with Termination Component 有权
标题翻译：带终端组件的定时存储系统
公开(公告)号：US20070247935A1
公开(公告)日：2007-10-25
申请号：US11767983
申请日：2007-06-25
申请人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
发明人： Frederick Ware , Ely Tsern , Richard Perego , Craig Hampel
IPC分类号： G11C7/00
CPC分类号： G11C7/1039 , G11C5/04 , G11C5/063 , G11C7/1048
摘要： A memory system having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data, associated with a write command, to the first memory device, and a second signal line coupled to the second memory device to provide second data, associated with the write command, to the second memory device. A control signal path is coupled to the first and second memory devices and the termination component such that the write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the termination component. A third signal line is provided to convey a clock signal that indicates when the write command propagating on the control signal path is to be sampled by the first and second memory devices.
摘要翻译：一种具有第一和第二存储器件和终端部件的存储器系统。第一信号线耦合到第一存储器设备，以向第一存储器设备提供与写命令相关联的第一数据，以及耦合到第二存储器设备以提供与写命令相关联的第二数据的第二信号线，到第二存储设备。控制信号路径被耦合到第一和第二存储器件和终端部件，使得在到达终端部件之前，在控制信号路径上传播的写入命令传播通过第一存储器件和第二存储器件。提供第三信号线来传送时钟信号，该时钟信号指示在控制信号路径上传播的写入命令何时被第一和第二存储器件采样。

30. 发明申请

US20050132158A1 Memory device signaling system and method with independent timing calibration for parallel signal paths 有权
标题翻译：用于并行信号路径的独立定时校准的存储器件信号系统和方法
公开(公告)号：US20050132158A1
公开(公告)日：2005-06-16
申请号：US11039447
申请日：2005-01-18
申请人： Craig Hampel , Richard Perego , Stefanos Sidiropoulos , Ely Tsern , Fredrick Ware
发明人： Craig Hampel , Richard Perego , Stefanos Sidiropoulos , Ely Tsern , Fredrick Ware
IPC分类号： G11C7/10 , G11C7/22 , G11C11/4078 , H04L7/00 , G06F12/00
CPC分类号： G11C11/4076 , G06F3/061 , G06F3/0629 , G06F3/0671 , G06F12/0246 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222 , G11C11/40611 , G11C11/4072 , G11C11/4078 , G11C11/4093 , G11C21/00 , G11C2207/2254 , H04L7/0025 , H04L7/0079 , H04L7/0091
摘要： A memory system includes a memory controller and a memory component coupled to each other. The memory controller includes an interface to receive a first signal and a second signal from the memory component, wherein the first signal comprises a first symbol and the second signal comprises a second symbol. A first circuit of the memory controller receives the first signal by sampling the first symbol using a first timing offset relative to a reference clock signal, and a second circuit of the memory controller receives the second signal by sampling the second symbol using a second timing offset relative to the reference clock signal. The first timing offset is independent of the second timing offset.
摘要翻译：存储器系统包括彼此耦合的存储器控制器和存储器组件。存储器控制器包括用于从存储器组件接收第一信号和第二信号的接口，其中第一信号包括第一符号，第二信号包括第二符号。存储器控制器的第一电路通过使用相对于参考时钟信号的第一定时偏移对第一符号进行采样来接收第一信号，并且存储器控制器的第二电路通过使用第二定时偏移量对第二符号进行采样来接收第二信号相对于参考时钟信号。第一定时偏移与第二定时偏移无关。

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