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    • 21. 发明授权
    • Method to form a low parasitic capacitance pseudo-SOI CMOS device
    • 形成低寄生电容伪SOI CMOS器件的方法
    • US06403485B1
    • 2002-06-11
    • US09846177
    • 2001-05-02
    • Elgin QuekRavi SundaresanYang PanJames Lee Yong MengYing KeungYelehanka Ramachandramurthy PradeepJia Zhen ZhengLap Chan
    • Elgin QuekRavi SundaresanYang PanJames Lee Yong MengYing KeungYelehanka Ramachandramurthy PradeepJia Zhen ZhengLap Chan
    • H01L21302
    • H01L21/76895
    • A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and associated SID extensions are fabricated in and on the substrate in the active regions wherein a hard mask layer overlies each of the gate electrodes. Dielectric spacers are formed on sidewalls of each of the gate electrodes. A polysilicon layer is deposited overlying the gate electrodes and the substrate. The polysilicon layer is polished back with a polish stop at the hard mask layer. The polysilicon layer is etched back whereby the polysilicon layer is recessed with respect to the gate electrodes. Thereafter, the polysilicon layer is etched away overlying the STI regions where a separation between adjacent active areas is desired. If a local interconnect is desired between adjacent active areas, the polysilicon layer is not etched away overlying the STI region separating those active areas. The hard mask layer is removed. Ions are implanted and driven in to form elevated S/D regions within the polysilicon layer adjacent to the gate electrodes to complete formation of transistors having elevated S/D regions.
    • 描述了一种形成具有可扩展的用于局部互连的源/漏(S / D)区域较高的伪SOI器件的方法。 分离相邻有源区的浅沟槽隔离(STI)区域设置在半导体衬底内。 多晶硅栅极电极和相关的SID延伸部分在其中硬掩模层覆盖每个栅极电极的有源区域内和衬底上制造。 在每个栅电极的侧壁上形成电介质间隔物。 沉积覆盖栅电极和衬底的多晶硅层。 在硬掩模层上用抛光光阑抛光多晶硅层。 多晶硅层被回蚀,由此多晶硅层相对于栅电极凹陷。 此后,将多晶硅层蚀刻掉,覆盖STI区域,其中期望相邻的有源区域之间的间隔。 如果在相邻的有源区域之间需要局部互连,则多晶硅层不会被覆盖在分离这些有源区域的STI区域之上。 去除硬掩模层。 离子被植入和驱动以在与栅电极相邻的多晶硅层内形成升高的S / D区,以完成具有升高的S / D区的晶体管的形成。
    • 24. 发明授权
    • Process having high tolerance to buried contact mask misalignment by
using a PSG spacer
    • 通过使用PSG间隔物对掩埋接触掩模未对准具有高耐受性的工艺
    • US5742088A
    • 1998-04-21
    • US837486
    • 1997-04-18
    • Yang PanLap ChanRavi Sundaresan
    • Yang PanLap ChanRavi Sundaresan
    • H01L21/74H01L29/08H01L27/11H01L29/40
    • H01L21/743
    • A new method of forming improved buried contact junctions is described. A layer of polysilicon overlying gate silicon oxide is provided over the surface of a semiconductor substrate and etched away to provide an opening to the substrate where a planned buried contact junction will be formed. A second doped polysilicon layer and a tungsten silicide layer are deposited and patterned to provide gate electrodes and a contact overlying the planned buried contact junction and providing an opening to the substrate where a planned source/drain region will be formed adjoining the planned buried contact junction and wherein a portion of the polysilicon layer not at the polysilicon contact remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the planned buried contact junction. A doped glasseous layer is deposited overlying the patterned tungsten silicide/polysilicon layer and within the trench, then isotropically etched away until it remains only partially filling the trench. The substrate is oxidized to drive-in dopant from the doped glasseous layer within the trench into the surrounding substrate. Ions are implanted to form the planned source/drain region. Dopant is outdiffused from the second polysilicon layer to form the planned buried contact junction wherein the dopant surrounding the trench provides a conduction channel between the source/drain region and the adjoining buried contact junction.
    • 描述了形成改进的埋入接点的新方法。 在半导体衬底的表面上提供覆盖栅极氧化硅的多晶硅层,并被蚀刻掉以提供到衬底的开口,其中将形成预定的埋入接触结。 第二掺杂多晶硅层和硅化钨层被沉积并图案化以提供栅极电极和覆盖在计划的埋入接触结上的触点,并提供到衬底的开口,其中将形成预定的源极/漏极区域邻接计划的埋入接触结 并且其中不在多晶硅接触处的多晶硅层的一部分保留为残留物。 残留物被蚀刻掉,由此在规划的源极/漏极区域和计划的埋入接触结的接合处将沟槽蚀刻到衬底中。 在图案化的硅化钨/多晶硅层上并在沟槽内沉积掺杂的硅酸盐层,然后各向同性地蚀刻掉,直到其仅部分地填充沟槽。 衬底被氧化成驱动掺杂剂从沟槽内的掺杂的玻璃质层进入周围的衬底。 植入离子以形成规划的源/漏区。 掺杂剂从第二多晶硅层向外扩散以形成计划的埋入接触结,其中围绕沟槽的掺杂剂在源极/漏极区域和相邻的掩埋接触结点之间提供导电沟道。
    • 25. 发明授权
    • Process having high tolerance to buried contact mask misalignment by
using a PSG spacer
    • 通过使用PSG间隔物对掩埋接触掩模未对准具有高耐受性的工艺
    • US5652152A
    • 1997-07-29
    • US636086
    • 1996-04-22
    • Yang PanLap ChanRavi Sundaresan
    • Yang PanLap ChanRavi Sundaresan
    • H01L21/74H01L21/441
    • H01L21/743
    • A new method of forming improved buried contact junctions is described. A layer of polysilicon overlying gate silicon oxide is provided over the surface of a semiconductor substrate and etched away to provide an opening to the substrate where a planned buried contact junction will be formed. A second doped polysilicon layer and a tungsten silicide layer are deposited and patterned to provide gate electrodes and a contact overlying the planned buried contact junction and providing an opening to the substrate where a planned source/drain region will be formed adjoining the planned buried contact junction and wherein a portion of the polysilicon layer not at the polysilicon contact remains as residue. The residue is etched away whereby a trench is etched into the substrate at the junction of the planned source/drain region and the planned buried contact junction. A doped glasseous layer is deposited overlying the patterned tungsten silicide/polysilicon layer and within the trench, then isotropically etched away until it remains only partially filling the trench. The substrate is oxidized to drive-in dopant from the doped glasseous layer within the trench into the surrounding substrate. Ions are implanted to form the planned source/drain region. Dopant is outdiffused from the second polysilicon layer to form the planned buried contact junction wherein the dopant surrounding the trench provides a conduction channel between the source/drain region and the adjoining buried contact junction.
    • 描述了形成改进的埋入接点的新方法。 在半导体衬底的表面上提供覆盖栅极氧化硅的多晶硅层,并被蚀刻掉以提供到衬底的开口,其中将形成预定的埋入接触结。 第二掺杂多晶硅层和硅化钨层被沉积并图案化以提供栅极电极和覆盖在计划的埋入接触结上的触点,并提供到衬底的开口,其中将形成预定的源极/漏极区域邻接计划的埋入接触结 并且其中不在多晶硅接触处的多晶硅层的一部分保留为残留物。 残留物被蚀刻掉,由此在规划的源极/漏极区域和计划的埋入接触结的接合处将沟槽蚀刻到衬底中。 在图案化的硅化钨/多晶硅层上并在沟槽内沉积掺杂的硅酸盐层,然后各向同性地蚀刻掉,直到其仅部分地填充沟槽。 衬底被氧化成驱动掺杂剂从沟槽内的掺杂的玻璃质层进入周围的衬底。 植入离子以形成规划的源/漏区。 掺杂剂从第二多晶硅层向外扩散以形成计划的埋入接触结,其中围绕沟槽的掺杂剂在源极/漏极区域和相邻的掩埋接触结点之间提供导电沟道。