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21. 发明授权

US06640309B2 Computer system providing low skew clock signals to a synchronous memory unit 有权
公开(公告)号：US06640309B2
公开(公告)日：2003-10-28
申请号：US10005593
申请日：2001-10-26
申请人： Drew G. Doblar , Han Y. Ko
发明人： Drew G. Doblar , Han Y. Ko
IPC分类号： G06F104
CPC分类号： G11C5/063 , G11C7/22 , G11C7/222
摘要： A computer system is described including a processor for executing instructions, a memory module for storing instructions and data, and a memory controller coupled between the processor and the memory module. The memory controller provides a differential clock signal and memory access signals which are routed to the memory module. The memory module includes multiple memory devices coupled to a clock buffer. The clock buffer produces a new single-ended “regenerated” clock signal from the differential clock signal. The clock buffer includes an input buffer circuit and a phase-locked loop (PLL). The input buffer circuit receives the differential clock signal from the memory controller and produces a single-ended reference clock signal from the differential clock signal. The PLL produces the regenerated clock signal substantially at the same frequency of, and in synchronization with, the single-ended reference clock signal produced by the input buffer circuit. Each of the multiple memory devices is coupled to receive the regenerated clock signal, and the operations of the multiple memory devices are synchronized to the regenerated clock signal. The multiple memory devices within the memory module may be coupled to receive the memory access signals produced by the memory controller, and may store data or retrieve data in response to the memory access signals and the regenerated clock signal. The multiple memory devices may include synchronous dynamic random access memory (SDRAM) devices, and the memory module may be a dual in-line memory module (DIMM).

22. 发明授权

US06614862B1 Encoded clocks to distribute multiple clock signals to multiple devices in a computer system 有权
标题翻译：编码时钟将多个时钟信号分配到计算机系统中的多个设备
公开(公告)号：US06614862B1
公开(公告)日：2003-09-02
申请号：US09476721
申请日：1999-12-30
申请人： Drew G. Doblar
发明人： Drew G. Doblar
IPC分类号： H04L700
CPC分类号： G06F1/10 , G06F1/06 , H03L7/06
摘要： An apparatus and method for distributing multiple clock signals to multiple devices using an encoded clock signal is provided. A source clock signal can be encoded to result in an encoded system clock. The encoded system clock can be distributed to multiple devices in a computer system. The devices can decode the encoded system clock signal to generate a system clock signal and a global clock signal. The system clock signal and the global clock signal can then be distributed to their respective clock loads on each device. In certain embodiments, additional information, such as state information, can be encoded into the encoded system clock. A device can be configured to decode the additional information and can alter its state accordingly.
摘要翻译：提供了一种使用编码时钟信号将多个时钟信号分配到多个设备的装置和方法。源时钟信号可以被编码以产生编码的系统时钟。编码的系统时钟可以分配到计算机系统中的多个设备。器件可以解码编码的系统时钟信号，以产生系统时钟信号和全局时钟信号。然后系统时钟信号和全局时钟信号可以分配到每个设备上的各自的时钟负载。在某些实施例中，诸如状态信息的附加信息可被编码到编码的系统时钟中。可以将设备配置为对附加信息进行解码，并可以相应地改变其状态。

23. 发明授权

US06194969B1 System and method for providing master and slave phase-aligned clocks 有权
标题翻译：提供主和从相对齐时钟的系统和方法
公开(公告)号：US06194969B1
公开(公告)日：2001-02-27
申请号：US09314812
申请日：1999-05-19
申请人： Drew G. Doblar
发明人： Drew G. Doblar
IPC分类号： H03L707
CPC分类号： G06F11/1604 , G06F1/04 , G06F11/20
摘要： A system and method for providing master and slave phase-aligned clocks. Upon a failure of a master clock signal, the system switches over to a slave clock signal in phase alignment with the master clock signal. The master clock signal is from a first clock source, while the slave clock signal is from a second clock source. The second clock source comprises a phase locked loop (PLL) including a switch, which is coupled to selectively provide a control signal to a voltage controlled oscillator (VCO). The switch may also provide a reference control voltage to the VCO. The first clock source may be on a first clock board, and the second clock source may be on a second clock board. The clock boards are preferably hot swappable. The first clock board may be removed from the system, such as upon a failure, and a third clock board placed in the system. The second clock board is switched from being the slave clock source to the master clock source, while the third clock board is configured to operate as the slave clock source. The method provides a first clock signal as a master clock signal. A second clock signal is provided as a slave clock signal, with the slave clock signal phase aligned with the master clock signal. Upon a failure of either the master clock signal or the slave clock signal, a user is notified of the failure. Upon the failure of the first clock signal, the second clock signal is switched in place of the first clock signal as the master clock signal. Clock switching is automatic and does not interrupt or interfere with operation of the computer system.
摘要翻译：一种用于提供主和从相对准时钟的系统和方法。在主时钟信号故障时，系统切换到与时钟信号相位对准的从时钟信号。主时钟信号来自第一个时钟源，而从时钟信号来自第二个时钟源。第二时钟源包括包括开关的锁相环（PLL），其被耦合以选择性地向压控振荡器（VCO）提供控制信号。开关还可以向VCO提供参考控制电压。第一时钟源可以在第一时钟板上，并且第二时钟源可以在第二时钟板上。时钟板最好是热插拔。可以将第一个时钟板从系统中移除，例如故障时，以及放置在系统中的第三个时钟板。第二个时钟板从从时钟源切换到主时钟源，而第三个时钟板被配置为从时钟源。该方法提供第一时钟信号作为主时钟信号。第二个时钟信号被提供为从时钟信号，从时钟信号与主时钟信号相对齐。在主时钟信号或从时钟信号失败时，向用户通知故障。当第一时钟信号发生故障时，第二时钟信号被切换以代替第一时钟信号作为主时钟信号。时钟切换是自动的，不会中断或干扰计算机系统的操作。

24. 发明授权

US5970070A Communication controllers and methods therefor 失效
标题翻译：通信控制器及其方法
公开(公告)号：US5970070A
公开(公告)日：1999-10-19
申请号：US915286
申请日：1997-08-20
申请人： Kin M. Ho , David C. Banks , John C. Schell , Tai Quan , Teshager Tesfaye , Kenneth A. Schmahl , Matthew J. Tedone , Drew G. Doblar
发明人： Kin M. Ho , David C. Banks , John C. Schell , Tai Quan , Teshager Tesfaye , Kenneth A. Schmahl , Matthew J. Tedone , Drew G. Doblar
IPC分类号： G06F13/38 , H04J3/02
CPC分类号： G06F13/385
摘要： A method, in a host adapter circuit configured for coupling a host electronic device with one of a fiber channel loop and a point-to-point communication channel, for receiving data at the host adapter circuit from one of the fiber channel loop and the point-to-point communication channel. The method includes providing a selectable control signal configured for indicating whether the host adapter circuit is coupled to the fiber channel loop or the point-to-point communication channel. The method further includes providing a front-end receive circuit. The front-end receive circuit is configured for coupling with an input data port. The input data port represents one of the fiber channel loop and the point-to-point communication channel. The method also includes coupling the front-end receive circuit with the selectable control signal. Additionally, the method includes coupling an output of the front-end receive circuit with a decoder of the host adapter circuit, wherein the front-end receive circuit is configured to process, responsive to the selectable control signal, either fiber channel loop data from the fiber channel loop or point-to-point data from the point-to-point communication channel from the input data port to provide parallel data having a predefined size to the decoder circuit.
摘要翻译：一种主机适配器电路中的方法，所述主机适配器电路被配置为将主机电子设备与光纤通道环路和点对点通信信道中的一个耦合，用于从所述主机适配器电路接收来自所述光纤通道环路和所述点对点通信通道。该方法包括提供可选择的控制信号，其被配置用于指示主机适配器电路是否耦合到光纤通道环路或点到点通信信道。该方法还包括提供前端接收电路。前端接收电路被配置为与输入数据端口耦合。输入数据端口表示光纤通道环路和点到点通信信道之一。该方法还包括将前端接收电路与可选择的控制信号相耦合。此外，该方法包括将前端接收电路的输出与主机适配器电路的解码器耦合，其中前端接收电路被配置为响应于可选择的控制信号处理来自所述主机适配器电路的光纤通道环路数据光纤通道环路或点对点数据从输入数据端口到点对点通信信道，以向解码器电路提供具有预定义大小的并行数据。

25. 发明授权

US08513831B2 Autonomous control in current share power supplies 有权
标题翻译：当前共享电源的自主控制
公开(公告)号：US08513831B2
公开(公告)日：2013-08-20
申请号：US12886730
申请日：2010-09-21
申请人： Michael Bushue , Drew G. Doblar
发明人： Michael Bushue , Drew G. Doblar
IPC分类号： H02J1/10
CPC分类号： H02J1/102 , H02J3/46 , H02J9/005 , H02M1/4225 , Y02B70/126 , Y10T307/50 , Y10T307/696
摘要： A method for autonomous control by a power supply unit (PSU) among a number of current share PSUs in a power supply system. The method includes: Receiving input power from a power input feed; setting a mode of the PSU to ON; receiving a first controlled signal including a first number of IStar modes and thresholds; receiving a first activation signal activating IStar in the PSU; receiving a second controlled signal comprising a first voltage; determining that the first voltage is less than a first Active standby OFF threshold for an IStar mode of Active standby OFF; setting the IStar mode for the PSU to Active standby OFF; receiving a third controlled signal that includes a second voltage; determining that the second voltage is greater than a first Active ON threshold for an IStar mode of Active ON; and setting the IStar mode for the PSU to Active ON.
摘要翻译：一种供电系统中多个当前共享PSU中的电源单元（PSU）的自主控制的方法。该方法包括：从电源输入馈电接收输入电源; 将PSU的模式设置为ON; 接收包括第一数量的IStar模式和阈值的第一受控信号; 接收在PSU中激活IStar的第一激活信号; 接收包括第一电压的第二受控信号; 确定第一电压小于用于主动待机OFF的IStar模式的第一活动待机OFF阈值; 将PSU的IStar模式设置为主动待机OFF; 接收包括第二电压的第三受控信号; 确定所述第二电压大于用于激活ON的IStar模式的第一有效开启阈值; 并将PSU的IStar模式设置为“有效”。

26. 发明申请

US20120033685A1 SERIAL LINK VOLTAGE MARGIN DETERMINATION IN MISSION MODE 有权
标题翻译：在任务模式下串行链路电压测量
公开(公告)号：US20120033685A1
公开(公告)日：2012-02-09
申请号：US12850535
申请日：2010-08-04
申请人： Drew G. Doblar , Dawei Huang , Deqiang Song
发明人： Drew G. Doblar , Dawei Huang , Deqiang Song
IPC分类号： H04J3/04 , G01R19/00
CPC分类号： H04L25/03057 , H04L25/061 , H04L25/14
摘要： This disclosure describes systems and methods for determining a voltage margin (or margin) of a serializer/deserializer (SerDes) receiver in mission mode using a SerDes receiver. This is done by time-division multiplexing a margin determination and a tap weight adaptation onto the same hardware (or software, or combination of hardware and software). In other words, some parts of a SerDes receiver (e.g., an error slicer and an adaptation module) can be used for two different tasks at different times without degrading the effectiveness or bandwidth of the receiver. Hence, the disclosed systems and methods allow a SerDes receiver to determine the SerDes margin in mission mode and without any additional hardware or circuitry on the receiver chip.
摘要翻译：本公开描述了使用SerDes接收机在任务模式下确定串行器/解串器（SerDes）接收器的电压余量（或余量）的系统和方法。这通过在相同的硬件（或软件或硬件和软件的组合）上进行裕度确定和抽头权重适配的时分复用来完成。换句话说，SerDes接收机的一些部分（例如，错误限制器和适配模块）可以在不同的时间用于两个不同的任务，而不降低接收机的有效性或带宽。因此，所公开的系统和方法允许SerDes接收机在任务模式下确定SerDes余量，并且在接收器芯片上没有任何额外的硬件或电路。

27. 发明申请

US20110261900A1 MECHANISM FOR CONSTRUCTING AN OVERSAMPLED WAVEFORM FOR A SET OF SIGNALS RECEIVED BY A RECEIVER 有权
标题翻译：用于构造接收器接收到的一组信号的OVERSAMPED WAVEFORM的机制
公开(公告)号：US20110261900A1
公开(公告)日：2011-10-27
申请号：US13175589
申请日：2011-07-01
申请人： Deqiang Song , Dawei Huang , Drew G. Doblar , Michael Stephen Harwood , Nirmal C. Warke
发明人： Deqiang Song , Dawei Huang , Drew G. Doblar , Michael Stephen Harwood , Nirmal C. Warke
IPC分类号： H04L27/00
CPC分类号： H04L25/068
摘要： A mechanism is provided for constructing an oversampled waveform for a set of incoming signals received by a receiver. In one implementation, the oversampled waveform is constructed by way of cooperation between the receiver and a waveform construction mechanism (WCM). The receiver receives the incoming signals, samples a subset of the incoming signals at a time, stores the subsets of sample values into a set of registers, and subsequently provides the subsets of sample values to the WCM. The WCM in turn sorts through the subsets of sample values, organizes them into proper orders, and “stitches” them together to construct the oversampled waveform for the set of incoming signals. With proper cooperation between the receiver and the WCM, and with proper processing logic on the WCM, it is possible to construct the oversampled waveform for the incoming signals without requiring large amounts of resources on the receiver.
摘要翻译：提供了一种用于为接收机接收的一组输入信号构造过采样波形的机制。在一个实现中，过采样波形通过接收器和波形构造机构（WCM）之间的协作来构造。接收机接收输入信号，一次对入局信号的子集进行采样，将样本值的子集存储到一组寄存器中，随后将样本值的子集提供给WCM。 WCM依次对样本值的子集进行排序，将它们组织成正确的顺序，并将它们“缝合”在一起，以构成输入信号集合的过采样波形。通过接收机和WCM之间的适当协作，并且在WCM上具有适当的处理逻辑，可以为输入信号构造过采样波形，而不需要接收机上的大量资源。

28. 发明授权

US08000426B2 Mechanism for constructing an oversampled waveform for a set of signals received by a receiver 有权
标题翻译：用于为接收机接收的一组信号构造过采样波形的机制
公开(公告)号：US08000426B2
公开(公告)日：2011-08-16
申请号：US12053121
申请日：2008-03-21
申请人： Deqiang Song , Dawei Huang , Drew G. Doblar , Michael Stephen Harwood , Nirmal C. Warke
发明人： Deqiang Song , Dawei Huang , Drew G. Doblar , Michael Stephen Harwood , Nirmal C. Warke
IPC分类号： H04L7/00
CPC分类号： H04L25/068
摘要： A mechanism is provided for constructing an oversampled waveform for a set of incoming signals received by a receiver. In one implementation, the oversampled waveform is constructed by way of cooperation between the receiver and a waveform construction mechanism (WCM). The receiver receives the incoming signals, samples a subset of the incoming signals at a time, stores the subsets of sample values into a set of registers, and subsequently provides the subsets of sample values to the WCM. The WCM in turn sorts through the subsets of sample values, organizes them into proper orders, and “stitches” them together to construct the oversampled waveform for the set of incoming signals. With proper cooperation between the receiver and the WCM, and with proper processing logic on the WCM, it is possible to construct the oversampled waveform for the incoming signals without requiring large amounts of resources on the receiver.
摘要翻译：提供了一种用于为接收机接收的一组输入信号构造过采样波形的机制。在一个实现中，过采样波形通过接收器和波形构造机构（WCM）之间的协作来构造。接收机接收输入信号，一次对入局信号的子集进行采样，将样本值的子集存储到一组寄存器中，随后将样本值的子集提供给WCM。 WCM依次对样本值的子集进行排序，将它们组织成正确的顺序，并将它们“缝合”在一起，以构成输入信号集合的过采样波形。通过接收机和WCM之间的适当协作，并且在WCM上具有适当的处理逻辑，可以为输入信号构造过采样波形，而不需要接收机上的大量资源。

29. 发明申请

US20110107292A1 Extraction of Component Models from PCB Channel Scattering Parameter Data by Stochastic Optimization 有权
标题翻译：通过随机优化从PCB通道散射参数数据中提取组件模型
公开(公告)号：US20110107292A1
公开(公告)日：2011-05-05
申请号：US12608364
申请日：2009-10-29
申请人： Juyoung Lee , Drew G. Doblar
发明人： Juyoung Lee , Drew G. Doblar
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G01R23/163 , G06F2217/10 , G06F2217/82
摘要： Various embodiments herein include one or more of systems, methods, software, and/or data structures to extract models of components (e.g., vias and traces) for PCB channels from measurements (or simulations) taken from physical PCB channels. By applying stochastic optimization to measurements of two PCB channels having different channel lengths, s-matrices (e.g., two-port, four-port, and the like) of the components of a PCB channel may be accurately determined by searching the multi-dimensional parameter space for parameters that comply with the measured values. Once the models for the components have been accurately determined, they may be utilized in constructing a model library that includes component models and is based on physical measurement data.
摘要翻译：本文的各种实施例包括从从物理PCB通道获取的测量（或模拟）中提取用于PCB通道的组件（例如，通孔和迹线）的模型的系统，方法，软件和/或数据结构中的一个或多个。通过对具有不同信道长度的两个PCB信道的测量应用随机优化，可以通过搜索多维度来准确地确定PCB信道的组件的s矩阵（例如，两端口，四端口等）符合测量值的参数的参数空间。一旦组件的模型已被准确地确定，它们可以用于构建包括组件模型并且基于物理测量数据的模型库。

30. 发明申请

US20100208855A1 SYSTEM AND METHOD OF ADAPTING PRECURSOR TAP COEFFICIENT 有权
标题翻译：系统和方法适应前提条纹系数
公开(公告)号：US20100208855A1
公开(公告)日：2010-08-19
申请号：US12388223
申请日：2009-02-18
申请人： Dawei Huang , Deqiang Song , Jianghui Su , Drew G. Doblar
发明人： Dawei Huang , Deqiang Song , Jianghui Su , Drew G. Doblar
IPC分类号： H04L7/00
CPC分类号： H04L7/0062
摘要： A system and methods for recovering data from an input data signal are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver uses an adaptive algorithm to determine update signals for a pre-cursor tap coefficient of the FIR based on samples taken from the received data signal and conveys the update signals to the FIR. To generate update signals, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel. The phase is based on a clock recovered from the data signal. The update signals increase or decrease a pre-cursor tap coefficient setting in response to determining that the phase corresponds to a point earlier or later, respectively, than the peak amplitude of the channel's pulse response.
摘要翻译：公开了一种从输入数据信号中恢复数据的系统和方法。该系统包括一个发射器，用于通过一个通道将一个由有限脉冲响应（FIR）滤波器滤波的数据信号传送到一个接收器。接收机使用自适应算法，基于从接收到的数据信号中取出的样本来确定FIR的前置光标抽头系数的更新信号，并将更新信号传送到FIR。为了产生更新信号，接收机以被估计为对应于信道的脉冲响应的峰值幅度的相位对数据信号进行采样。该相位基于从数据信号恢复的时钟。响应于确定相位对应于分别比通道的脉冲响应的峰值幅度更早或更晚的点，更新信号增加或减少前置光标抽头系数设置。

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