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21. 发明申请

US20050156629A1 HIGH CURRENT 5V TOLERANT BUFFER USING A 2.5 VOLT POWER SUPPLY 失效
标题翻译：使用2.5伏电源的高电流5V耐受缓冲器
公开(公告)号：US20050156629A1
公开(公告)日：2005-07-21
申请号：US10759253
申请日：2004-01-20
申请人： Carol Huber , Bernard Morris , Makeshwar Kothandaraman , Yehuda Smooha
发明人： Carol Huber , Bernard Morris , Makeshwar Kothandaraman , Yehuda Smooha
IPC分类号： H03K19/003 , H03K19/0175
CPC分类号： H03K19/00315 , H03K2217/0018
摘要： Using at best a 2.5V nominal power supply, 3.3V technology can be used to implement a 5V tolerant open drain output buffer. High voltage and/or current tolerance is achieved with only the 2.5V power supply. A p-channel FET transistor is connected between a power supply and a node, which in turn is connected to a node between two series output FET transistors. The first transistor is connected between the PAD and node, and the second transistor is connected between the node and ground. The gate of the second transistor is driven from another node formed between a series string of a p-channel FET transistor and an n-channel FET transistor. The other side of the first transistor is connected to the power supply, and the other side of the second transistor is connected to ground. The gates of the transistors the inverter are tied together and driven by an applied signal.
摘要翻译：最多使用2.5V标称电源，3.3V技术可用于实现5V容限的开漏输出缓冲器。仅使用2.5V电源即可实现高电压和/或电流公差。 p沟道FET晶体管连接在电源和节点之间，而节点又连接到两个串联输出FET晶体管之间的节点。第一晶体管连接在PAD和节点之间，第二晶体管连接在节点和地之间。第二晶体管的栅极由形成在p沟道FET晶体管的串联串和n沟道FET晶体管之间的另一个节点驱动。第一晶体管的另一侧连接到电源，第二晶体管的另一侧连接到地。晶体管的栅极将反相器连接在一起并由施加的信号驱动。

22. 发明申请

US20050110511A1 Integrated circuit with controllable test access to internal analog signal pads of an area array 有权
标题翻译：集成电路，具有对区域阵列的内部模拟信号焊盘的可测试访问
公开(公告)号：US20050110511A1
公开(公告)日：2005-05-26
申请号：US10719193
申请日：2003-11-21
申请人： Thaddeus Gabara , Carol Huber , Bernard Morris
发明人： Thaddeus Gabara , Carol Huber , Bernard Morris
IPC分类号： H01L27/00 , G01R31/28 , H01L21/66 , H01L21/822 , H01L27/04 , G01R31/02
CPC分类号： G01R31/2884
摘要： An integrated circuit die comprises an internal signal pad arranged at a location away from a periphery of the die, a peripheral signal pad arranged proximate the periphery of the die, and a switch coupled between the internal signal pad and the peripheral signal pad. The switch is configurable in at least a first state in which the internal signal pad is not operatively connected to the peripheral signal pad, and a second state in which the internal signal pad is operatively connected to the peripheral signal pad, responsive to a control signal having one of respective first and second signal characteristics. The switch is configured in the first state during normal operation of the integrated circuit die, and is configured in the second state to permit test access to the internal signal pad via the peripheral signal pad.
摘要翻译：集成电路管芯包括布置在远离管芯周边的位置处的内部信号焊盘，邻近管芯周边布置的外围信号焊盘以及耦合在内部信号焊盘和外围信号焊盘之间的开关。该开关可配置成至少第一状态，其中内部信号焊盘不可操作地连接到外围信号焊盘，而第二状态，其中内部信号焊盘可操作地连接到外围信号焊盘，响应控制信号具有各自的第一和第二信号特性之一。该开关在集成电路管芯的正常操作期间被配置为第一状态，并且被配置在第二状态以允许经由外围信号焊盘测试访问内部信号焊盘。

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