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21. 发明授权

US08341588B2 Semiconductor layer forming method and structure 有权
标题翻译：半导体层形成方法和结构
公开(公告)号：US08341588B2
公开(公告)日：2012-12-25
申请号：US12897021
申请日：2010-10-04
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： G06F15/04 , G06F17/50
CPC分类号： G06F17/5068 , G06F2217/72
摘要： A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures. The second semiconductor device comprises the additional structure layer located within the second insertion point location.
摘要翻译：一种形成和电气结构的方法。该方法包括确定第一半导体器件需要工程改变顺序（ECO）。确定实现ECO所需的附加结构层。选择用于将附加结构层插入第一半导体器件内的第一插入点位置。第一插入点位置与用于第二半导体器件的设计中的第二插入点位置相关联。根据第一ECO产生第二半导体器件。第二半导体器件包括第二结构。第二结构包括与第一半导体器件中的第一结构相同的结构。第二结构形成在第二半导体器件内的与包含第一结构的第一半导体器件中的位置相关联的位置。第二半导体器件包括位于第二插入点位置内的附加结构层。

22. 发明授权

US08060845B2 Minimizing impact of design changes for integrated circuit designs 有权
标题翻译：最大限度地减少设计变更对集成电路设计的影响
公开(公告)号：US08060845B2
公开(公告)日：2011-11-15
申请号：US12173222
申请日：2008-07-15
申请人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
发明人： Robert D. Herzl , Robert S. Horton , Kenneth A. Lauricella , David W. Milton , Clarence R. Ogilvie , Paul M. Schanely , Nitin Sharma , Tad J. Wilder , Charles B. Winn
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method is provided for updating an existing netlist to reflect a design change. A register transfer level (RTL) design incorporating the design change and the existing netlist are provided to a synthesis tool. The existing netlist is set to a read-only condition to prevent a change to the existing netlist. The design and the read-only existing netlist are processed with the synthesis tool reusing logic structures from the read-only existing netlist by performing an optimization of the design and the read-only existing netlist with an objective to minimize the design space. The optimization is constrained by the read-only existing netlist. A result is generated by the synthesis tool including the existing netlist and a new portion of a netlist reflecting the design change.
摘要翻译：提供了一种用于更新现有网表以反映设计变更的方法。将设计更改和现有网表的注册传输级别（RTL）设计提供给综合工具。现有的网表设置为只读条件，以防止更改现有的网表。通过执行设计优化和只读现有网表的综合工具对来自只读现有网表的逻辑结构进行重用，设计和只读现有网表被处理，目的是最小化设计空间。优化受只读现有网表约束。综合工具产生的结果包括现有网表和反映设计变更的网表的新部分。

23. 发明授权

US07996807B2 Integrated test waveform generator (TWG) and customer waveform generator (CWG), design structure and method 有权
标题翻译：集成测试波形发生器（TWG）和客户波形发生器（CWG），设计结构和方法
公开(公告)号：US07996807B2
公开(公告)日：2011-08-09
申请号：US12104461
申请日：2008-04-17
申请人： Gary D. Grise , Vikram Iyengar , David E. Lackey , David W. Milton
发明人： Gary D. Grise , Vikram Iyengar , David E. Lackey , David W. Milton
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F1/10 , G06F2217/62 , H03K5/156
摘要： Disclosed are embodiments of a clock generation circuit, a design structure for the circuit and an associated method that provide deskewing functions and that further provide precise timing for both testing and functional operations. Specifically, the embodiments incorporate a deskewer circuit that is capable of receiving waveform signals from both an external waveform generator and an internal waveform generator. The external waveform generator can generate and supply to the deskewer circuit a pair of waveform signals for functional operations. The internal waveform generator can be uniquely configured with control logic and counter logic for generating and supplying a pair of waveform signals to the deskewer circuit for any one of built-in self-test (BIST) operations, macro-test operations, other test operations or functional operations. The deskewer circuit can selectively gate an input clock signal with the waveform signals from either the external or internal waveform generator in order to generate the required output clock signal.
摘要翻译：公开了时钟发生电路的实施例，用于电路的设计结构和相关联的方法，其提供了偏移功能，并进一步为测试和功能操作提供精确的定时。具体地说，这些实施例结合了能够从外部波形发生器和内部波形发生器接收波形信号的偏移电路。外部波形发生器可以生成和提供一个用于功能操作的波形信号。内部波形发生器可以独特地配置控制逻辑和计数器逻辑，用于为内置自检（BIST）操作，宏测试操作，其他测试操作中的任何一个产生和提供一对波形信号到电路板电路或功能操作。该偏移电路可以使用来自外部或内部波形发生器的波形信号选择性地输入输入时钟信号，以便产生所需的输出时钟信号。

24. 发明授权

US07863949B2 Circuit and design structure for synchronizing multiple digital signals 有权
标题翻译：用于同步多个数字信号的电路和设计结构
公开(公告)号：US07863949B2
公开(公告)日：2011-01-04
申请号：US12759015
申请日：2010-04-13
申请人： David W. Milton
发明人： David W. Milton
IPC分类号： H03L7/00
CPC分类号： H03L7/00 , G06F5/06 , H04L7/033
摘要： Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical pipelined signal paths receive digital input signals. XOR gates are associated with each of the signal paths. Each XOR gate monitors activity in a given signal path and controls, directly or indirectly (depending upon the embodiment), advancement of signal processing in the other signal path(s) to ensure that, if warranted, output signals at the circuit output nodes are synchronized. In a two-signal path embodiment, advancement of signal processing in one signal path is triggered, whenever transitioning digital signals are detected within the other signal path. In an n-signal path advancement of signal processing is triggered in all signal paths, whenever transitioning digital signals are detected on at least one signal path.
摘要翻译：公开了一种电路，被配置为当希望在时钟域之间同时移动信号时，将来自不同异步时钟域的一个时钟域接收的多个信号同步。在电路中，多个基本相同的流水线信号路径接收数字输入信号。 XOR门与每个信号路径相关联。每个XOR门监视给定信号路径中的活动并且直接或间接地控制（取决于实施例），在另一个信号路径中提高信号处理，以确保如果有必要，在电路输出节点处的输出信号是同步在双信号路径实施例中，每当在另一个信号路径内检测到转换的数字信号时，触发一个信号路径中的信号处理的提前。无论何时在至少一个信号路径上检测到转换数字信号，在所有信号路径中触发信号处理的n信号通路。

25. 发明授权

US07240266B2 Clock control circuit for test that facilitates an at speed structural test 有权
标题翻译：用于测试的时钟控制电路，便于进行速度结构测试
公开(公告)号：US07240266B2
公开(公告)日：2007-07-03
申请号：US10906407
申请日：2005-02-18
申请人： Henry R. Farmer , Gary D. Grise , David W. Milton , Mark R. Taylor
发明人： Henry R. Farmer , Gary D. Grise , David W. Milton , Mark R. Taylor
IPC分类号： G01R31/28
CPC分类号： G01R31/31727 , G01R31/318533
摘要： When testing an ASIC using functional clocks, a control circuit at the clock root incorporates additional test logic in the root and a deskewer for clock control, giving rise to a very flexible control that can pass clock signals at a number of clock rates and can pass only a single clock edge, thereby permitting the passage of the required number of clock pulses for a test. The system uses the functional clock and the clock distribution tree designed into the ASIC.
摘要翻译：当使用功能时钟测试ASIC时，时钟根控制电路在根中包含额外的测试逻辑和用于时钟控制的调制台，从而产生非常灵活的控制，可以以多个时钟速率通过时钟信号，并且可以通过只有一个时钟沿，从而允许所需数量的时钟脉冲通过测试。该系统使用ASIC中设计的功能时钟和时钟分配树。

26. 发明授权

US06865502B2 Method and system for logic verification using mirror interface 失效
公开(公告)号：US06865502B2
公开(公告)日：2005-03-08
申请号：US09826035
申请日：2001-04-04
申请人： Robert J. Devins , Paul J. Ferro , Peter D. LaFauci , Kenneth A. Mahler , David W. Milton
发明人： Robert J. Devins , Paul J. Ferro , Peter D. LaFauci , Kenneth A. Mahler , David W. Milton
IPC分类号： G01R31/319 , G01R31/14 , G06F19/00
CPC分类号： G01R31/318357 , G01R31/319 , G06F17/5022
摘要： Verification of external interfaces of cores on system-on-chip (SOC) designs frequently entails the purchase of costly standardized software models to test the external interfaces. Typically, the standardized models provide more functionality than is needed. Instead of standardized models, test models may be developed and utilized, but this also incurs cost and delay. The present invention provides an efficient and economical alternative. A mirror interface, or copy of the external interface undergoing verification, is used with a standardized control mechanism to verify the external interface. Because all interface I/O connections can thereby be utilized, a cost-effective and highly reusable way of verifying such interfaces is provided.

27. 发明授权

US06539522B1 Method of developing re-usable software for efficient verification of system-on-chip integrated circuit designs 失效
标题翻译：开发可重用软件的方法，用于片上系统集成电路设计的有效验证
公开(公告)号：US06539522B1
公开(公告)日：2003-03-25
申请号：US09494907
申请日：2000-01-31
申请人： Robert J. Devins , Paul G. Ferro , Robert D. Herzl , Mark E. Kautzman , Kenneth A. Mahler , David W. Milton
发明人： Robert J. Devins , Paul G. Ferro , Robert D. Herzl , Mark E. Kautzman , Kenneth A. Mahler , David W. Milton
IPC分类号： G06F1750
CPC分类号： G01R31/318357 , G06F17/5022
摘要： A method for developing re-usable software for the efficient verification of system-on-chip (SOC) integrated circuit designs. The verification software is used to generate and apply test cases to stimulate components of a SOC design (“cores”) in simulation; the results are observed and used to de-bug the design. The software is hierarchical, implementing a partition between upper-level test application code which generates test cases and verifies results, and low-level device driver code which interfaces with a core being simulated, to apply the test case generated by the upper-level code on a hardware level of operations. Test application and supporting low-level device driver pairs are used and re-used to test their corresponding component cores throughout the SOC development process, by creating higher-level test control programs which control selected combinations of the already-developed test application and device driver programs to test combinations of SOC components. The method provides for the efficient verification of SOC designs and, consequently, a reduced time-to-market for SOC products, because as the verification software is developed and stored, it becomes possible to test increasingly complex core combinations by creating relatively few high-level test programs which re-use already-existing lower-level software. Ultimately, the task of verifying a complex SOC design may be simplified to developing a single chip-specific test program which selects from already-existing test application, device driver and test control programs to perform a realistic test of a chip-specific combination of cores.
摘要翻译：一种用于开发用于片上系统（SOC）集成电路设计的有效验证的可重用软件的方法。验证软件用于生成和应用测试用例，以刺激模拟中SOC设计（“核心”）的组件; 观察结果并用于对设计进行设计。该软件是分级的，实现生成测试用例的上级测试应用程序代码和验证结果之间的分区，以及与正在模拟的内核接口的低级设备驱动程序代码，以应用由上级代码生成的测试用例在硬件层面的操作。测试应用程序和支持低级设备驱动程序对被使用并重新用于在SOC开发过程中测试其相应的组件核心，通过创建更高级别的测试控制程序来控制已经开发的测试应用程序和设备驱动程序的选定组合测试SOC组件组合的程序。该方法提供SOC设计的有效验证，从而缩短了SOC产品的上市时间，因为随着验证软件的开发和存储，可以通过创建相对较少的高可用性测试来测试日益复杂的核心组合，重新使用已经存在的低级软件的级别测试程序。最终，可以简化验证复杂SOC设计的任务，以开发单个芯片特定的测试程序，该测试程序从已经存在的测试应用程序，设备驱动程序和测试控制程序中进行选择，以执行芯片特定的内核组合的现实测试。

28. 发明授权

US4873878A Apparatus for inspecting and hangering pants 失效
标题翻译：用于检查和悬挂裤子的装置
公开(公告)号：US4873878A
公开(公告)日：1989-10-17
申请号：US139293
申请日：1987-12-29
申请人： David W. Milton
发明人： David W. Milton
IPC分类号： D06F95/00 , D06H3/02 , D06H3/16 , G01N33/36
CPC分类号： G01N33/367 , D06F95/00 , D06H3/02 , D06H3/16
摘要： An apparatus for inspecting and hangering laundered pairs of pants comprises an inspection station, a hangering station and a take-away device. The inspection station includes a pants gripper which supports a pair of pants at the waist with the legs in an extended position to permit simultaneous visual and touch inspection of the pants, after which the pant legs are folded along their creases on a folding table. Hangers are delivered one at a time to a hanger catch plate at one end of the folding table which supports the hangers slightly beneath the plane of the tabletop. The pant legs are slid along the folding table and partially draped over the end of the table and the bottom wire of the hanger supported on the hanger catch plate. A take-away device contacts the hook portion of the hanger and lifts it upwardly, carrying the pants therewith, and then discharges the hangered pants onto a take-away rail for movement to another station for further processing.
摘要翻译：用于检查和悬挂洗衣裤的裤子的装置包括检查站，悬挂站和取出装置。检查站包括裤子夹持器，其在腰部支撑一条裤子，腿部处于延伸位置，以允许同时对裤子进行视觉和触摸检查，之后将裤腿沿着折痕折叠在折叠桌上。衣架一次送到折叠桌的一端的衣架扣板，其支撑在桌面平面下方的衣架。裤腿沿着折叠台滑动，并部分地覆盖在桌子的端部上，并且衣架的底部线材支撑在衣架卡扣板上。取出装置接触衣架的钩部并将其向上提起，携带裤子，然后将悬挂的裤子排出到取出轨道上，以便移动到另一站以进一步处理。

29. 发明授权

US09367493B2 Method and system of communicating between peer processors in SoC environment 有权
标题翻译：在SoC环境中对等处理器之间进行通信的方法和系统
公开(公告)号：US09367493B2
公开(公告)日：2016-06-14
申请号：US11275091
申请日：2005-12-09
申请人： Robert J. Devins , David W. Milton , Pascal A. Nsame
发明人： Robert J. Devins , David W. Milton , Pascal A. Nsame
IPC分类号： G06F15/173 , G06F13/24 , G06F15/17
CPC分类号： G06F13/24 , G06F15/17
摘要： A method and system comprises transferring data from a first processor to at least one pulse generator directly connected to an interrupt control of at least a second processor. The transferring of the data bypasses memory. The method further includes reading the transferred data directly from the at least one pulse generator by the at least a second processor.
摘要翻译：一种方法和系统包括将数据从第一处理器传送到直接连接到至少第二处理器的中断控制的至少一个脉冲发生器。数据传输绕过内存。该方法还包括由至少第二处理器直接从至少一个脉冲发生器读取传送的数据。

30. 发明授权

US08736340B2 Differential clock signal generator 有权
标题翻译：差分时钟信号发生器
公开(公告)号：US08736340B2
公开(公告)日：2014-05-27
申请号：US13534090
申请日：2012-06-27
申请人： David W. Milton
发明人： David W. Milton
IPC分类号： G06F1/10 , G06F1/06
CPC分类号： G06F1/10 , G06F1/06 , H03K5/156
摘要： Disclosed is a differential clock signal generator which processes a first differential clock signal using a combination of differential and non-differential components to generate a second differential clock signal. Specifically, the first differential clock signal is converted into a single-ended clock signal, which is used either by a finite state machine to generate two single-ended control signals or by a waveform generator to generate a single-ended waveform control signal. In any case, a deskewer, which comprises a pair of single-ended latches and either multiplexer(s) or logic gates, processes the first differential clock signal, the single-ended clock signal, and the control signal(s) in order to output a second differential clock signal that is different from the first differential clock signal in terms of delay and, optionally, frequency, but synchronously linked to it.
摘要翻译：公开了一种差分时钟信号发生器，其使用差分和非差分分量的组合来处理第一差分时钟信号，以产生第二差分时钟信号。特别地，第一差分时钟信号被转换为单端时钟信号，其由有限状态机使用以产生两个单端控制信号，或由波形发生器用于产生单端波形控制信号。在任何情况下，包括一对单端锁存器和多路复用器或逻辑门的电力负载器处理第一差分时钟信号，单端时钟信号和控制信号，以便在延迟和可选地频率上输出不同于第一差分时钟信号的第二差分时钟信号，但是与其同步地相关联。

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