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21. 发明授权

US6057597A Semiconductor package with pre-fabricated cover 有权
标题翻译：具有预制盖的半导体封装
公开(公告)号：US6057597A
公开(公告)日：2000-05-02
申请号：US172451
申请日：1998-10-14
申请人： Warren M. Farnworth , David R. Hembree , Derek Gochnour , Salman Akram , John O. Jacobson , James M. Wark , Steven G. Thummel
发明人： Warren M. Farnworth , David R. Hembree , Derek Gochnour , Salman Akram , John O. Jacobson , James M. Wark , Steven G. Thummel
IPC分类号： H01L23/04 , H01L23/10 , H01L23/12
CPC分类号： H01L23/10 , H01L23/04 , H01L2224/16 , H01L2224/48091 , H01L24/48 , H01L2924/00014 , H01L2924/01087 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195
摘要： A semiconductor package includes a substrate having one or more dice mounted thereto, and a cover adapted to protect and form a sealed space for the dice. The cover can be pre-fabricated of molded plastic, or stamped metal, and attached to the substrate using a cured seal. A hole can also be provided through the substrate to permit pressure equalization during formation of the seal. The cover can be prefabricated in an enclosed configuration for attachment directly to the substrate, or in a planar configuration for attachment to a peripheral ridge on the substrate. In either embodiment, the cover is removable to permit defective dice to be replaced or repaired.
摘要翻译：半导体封装包括具有安装在其上的一个或多个裸片的衬底和适于保护并形成用于裸片的密封空间的盖。盖可以用模制塑料或冲压金属预制，并使用固化的密封件附接到基底。还可以通过基底提供孔，以在形成密封期间允许压力平衡。盖可以以封闭构造预制成直接附接到基底，或者以平面构造附接到基底上的外围脊。在任一实施例中，盖可移动以允许更换或修理有缺陷的骰子。

22. 发明授权

US5962921A Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps 失效
标题翻译：互连具有凹入的接触构件和穿透刀片，用于测试具有接触凸块的半导体管芯和封装
公开(公告)号：US5962921A
公开(公告)日：1999-10-05
申请号：US829193
申请日：1997-03-31
申请人： Warren M. Farnworth , Derek Gochnour , Salman Akram
发明人： Warren M. Farnworth , Derek Gochnour , Salman Akram
IPC分类号： G01R1/04 , G01R1/067 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： G01R1/0466 , G01R1/0408 , H01L2224/0401 , H01L2224/05551 , H01L2224/16 , H01L2224/81136 , H01L2224/81385 , H01L2924/01004 , H01L2924/0102 , H01L2924/01021 , H01L2924/01037 , H01L2924/01057 , H01L2924/01077 , H01L2924/01079 , H01L2924/01087 , H01L2924/15311
摘要： An interconnect for establishing temporary electrical communication with semiconductor dice, or packages, having contact bumps is provided. The interconnect includes patterns of contact members adapted to receive the contact bumps. Each contact member includes a recess covered with a conductive layer in electrical communication with a conductor. The recesses include a peripheral edge sized to contact a range of bump sizes and to penetrate native oxide layers on the bumps. In addition, the contact members can include blades configured to penetrate into the bumps. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare dice or chip scale packages.
摘要翻译：提供了一种用于与半导体裸片或具有接触凸块的封装建立临时电气通信的互连。互连包括适于接收接触凸块的接触构件的图案。每个接触构件包括覆盖有与导体电连通的导电层的凹部。所述凹部包括尺寸适于接触一定范围的凸块尺寸并且穿透凸块上的自然氧化物层的外围边缘。此外，接触构件可以包括构造成穿透到凸块中的刀片。该互连可以用于晶片级测试系统中，用于测试包含在晶片上的裸片或用于测试裸裸片或芯片级封装的芯片级测试系统。

23. 发明申请

US20050191876A1 Spring element for use in an apparatus for attaching to a semiconductor and a method of making 失效
标题翻译：用于连接到半导体的装置中的弹簧元件和制造方法
公开(公告)号：US20050191876A1
公开(公告)日：2005-09-01
申请号：US11122626
申请日：2005-05-05
申请人： David Hembree , Salman Akram , Derek Gochnour
发明人： David Hembree , Salman Akram , Derek Gochnour
IPC分类号： G01R1/04 , H01R12/00
CPC分类号： G01R1/0466 , Y10T29/49117 , Y10T29/49147 , Y10T29/49149 , Y10T29/49153 , Y10T29/53209 , Y10T29/5323
摘要： A spring element used in a temporary package for testing semiconductors is provided. The spring element is compressed so as to press the semiconductor, either in the form of a bare semiconductor die or as part of a package, against an interconnect structure. The spring element is configured so that it provides sufficient pressure to keep the contacts on the semiconductor in electrical contact with the interconnect structure. Material is added and/or removed from the spring element so that it has the desired modulus of elasticity. The shape of the spring element may also be varied to change the modulus of elasticity, the spring constant, and the force transfer capabilities of the spring element.
摘要翻译：提供了用于测试半导体的临时封装中的弹簧元件。弹簧元件被压缩以将半导体以裸半导体管芯的形式或作为封装的一部分压在互连结构上。弹簧元件构造成使得其提供足够的压力以保持半导体上的触点与互连结构电接触。向弹簧元件添加和/或移除材料，使其具有所需的弹性模量。弹簧元件的形状也可以改变以改变弹性元件的弹性模量，弹簧常数和力传递能力。

24. 发明申请

US20050211236A1 Dicing saw with variable indexing capability 失效
标题翻译：具有可变索引能力的切割锯
公开(公告)号：US20050211236A1
公开(公告)日：2005-09-29
申请号：US11137048
申请日：2005-05-25
申请人： Salman Akram , Derek Gochnour , Michael Hess , David Hembree
发明人： Salman Akram , Derek Gochnour , Michael Hess , David Hembree
IPC分类号： B23P17/00 , B26D3/00 , B28D1/32 , B28D5/02 , H01L21/00 , H01L21/301 , H01L23/58 , H01L29/00 , H05K3/02 , H05K3/20 , H05K3/30
CPC分类号： H01L21/67092 , B28D5/024 , B28D5/029 , Y10T83/0222 , Y10T83/0363 , Y10T83/04 , Y10T83/0524 , Y10T83/7726 , Y10T83/7809 , Y10T83/7868
摘要： A saw for dicing substrates, such as semiconductor wafers, that has one or more variable indexing capabilities and two or more blades. One of the blades may be moved laterally or vertically, independent of one or more other blades.
摘要翻译：用于具有一个或多个可变分度能力的切割基板（例如半导体晶片）的锯和两个或更多个叶片。一个叶片可以横向或垂直地移动，而与一个或多个其它叶片无关。

25. 发明授权

US06232243B1 Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps 有权
标题翻译：互连具有凹入的接触构件和穿透刀片，用于测试具有接触凸块的半导体管芯和封装
公开(公告)号：US06232243B1
公开(公告)日：2001-05-15
申请号：US09226052
申请日：1999-01-05
申请人： Warren M. Farnworth , Derek Gochnour , Salman Akram
发明人： Warren M. Farnworth , Derek Gochnour , Salman Akram
IPC分类号： H01R3126
CPC分类号： G01R1/0466 , G01R1/0408 , H01L2224/0401 , H01L2224/05551 , H01L2224/16 , H01L2224/81136 , H01L2224/81385 , H01L2924/01004 , H01L2924/0102 , H01L2924/01021 , H01L2924/01037 , H01L2924/01057 , H01L2924/01077 , H01L2924/01079 , H01L2924/01087 , H01L2924/15311
摘要： An interconnect for establishing temporary electrical communication with semiconductor dice, or packages, having contact bumps is provided. The interconnect includes patterns of contact members adapted to receive the contact bumps. Each contact member includes a recess covered with a conductive layer in electrical communication with a conductor. The recesses include a peripheral edge sized to contact a range of bump sizes and to penetrate native oxide layers on the bumps. In addition, the contact members can include blades configured to penetrate into the bumps. The interconnect can be employed in a wafer level test system for testing dice contained on a wafer, or in a die level test system for testing bare dice or chip scale packages.
摘要翻译：提供了一种用于与半导体裸片或具有接触凸块的封装建立临时电气通信的互连。互连包括适于接收接触凸块的接触构件的图案。每个接触构件包括覆盖有与导体电连通的导电层的凹部。所述凹部包括尺寸适于接触一定范围的凸块尺寸并且穿透凸块上的自然氧化物层的外围边缘。此外，接触构件可以包括构造成穿透到凸块中的刀片。该互连可以用于晶片级测试系统中，用于测试包含在晶片上的裸片或用于测试裸裸片或芯片级封装的芯片级测试系统。

26. 发明授权

US06307394B1 Test carrier with variable force applying mechanism for testing semiconductor components 失效
公开(公告)号：US06307394B1
公开(公告)日：2001-10-23
申请号：US09231347
申请日：1999-01-13
申请人： Warren M. Farnworth , Salman Akram , James M. Wark , Derek Gochnour
发明人： Warren M. Farnworth , Salman Akram , James M. Wark , Derek Gochnour
IPC分类号： G01R3126
CPC分类号： G01R1/0466
摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for testing components using the carrier, are provided. The carrier includes a base, an interconnect for making temporary electrical connections with the component, and a force applying mechanism for biasing the component against the interconnect. The force applying mechanism includes an elastomeric biasing member adapted to apply a relatively large biasing force during assembly of the carrier and a smaller biasing force in the assembled carrier. The force applying mechanism also includes a pressure plate which can include a cushioning layer with a non-stick surface for contacting the component. In addition, the cushioning layer, and elastomeric biasing member can be made of conductive elastomers to provide an electrical path from a backside of the component.

27. 发明授权

US06297660B2 Test carrier with variable force applying mechanism for testing semiconductor components 失效
公开(公告)号：US06297660B2
公开(公告)日：2001-10-02
申请号：US09734514
申请日：2000-12-12
申请人： Warren M. Farnworth , Salman Akram , James M. Wark , Derek Gochnour
发明人： Warren M. Farnworth , Salman Akram , James M. Wark , Derek Gochnour
IPC分类号： G01R3126
CPC分类号： G01R1/0466
摘要： A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for testing components using the carrier, are provided. The carrier includes a base, an interconnect for making temporary electrical connections with the component, and a force applying mechanism for biasing the component against the interconnect. The force applying mechanism includes an elastomeric biasing member adapted to apply a relatively large biasing force during assembly of the carrier and a smaller biasing force in the assembled carrier. The force applying mechanism also includes a pressure plate which can include a cushioning layer with a non-stick surface for contacting the component. In addition, the cushioning layer, and elastomeric biasing member can be made of conductive elastomers to provide an electrical path from a backside of the component.

28. 发明授权

US06300782B1 System for testing semiconductor components having flexible interconnect 失效
标题翻译：用于测试具有灵活互连的半导体元件的系统
公开(公告)号：US06300782B1
公开(公告)日：2001-10-09
申请号：US09872434
申请日：2001-06-04
申请人： David R. Hembree , Derek Gochnour
发明人： David R. Hembree , Derek Gochnour
IPC分类号： G01R3126
CPC分类号： G01R1/07307 , G01R1/06738 , G01R1/06761 , H01L2224/16237 , H01L2224/8114 , H01R13/24 , Y10T29/49155 , Y10T29/49204 , Y10T29/49208 , Y10T29/49224
摘要： A system for testing semiconductor components includes a testing apparatus, such as a test carrier for discrete components, or a wafer prober for wafer sized components The system also includes an interconnect for electrically engaging the components. The interconnect includes a thinned substrate, and first contacts on the substrate for electrically engaging second contacts on the components. The thinned substrate has a thickness that is substantially less than a thickness of the components being tested. The thinned substrate can flex upon application of a biasing force by the testing apparatus, permitting the first contacts to move in the z-direction to accommodate variations in the planarity of the second contacts.
摘要翻译：用于测试半导体部件的系统包括诸如用于分立组件的测试载体的测试装置或用于晶片尺寸部件的晶片探测器。该系统还包括用于电耦合部件的互连。互连包括薄化的衬底，并且在衬底上的第一接触件用于电接合部件上的第二触点。薄化的衬底的厚度实质上小于被测试组件的厚度。减薄的基板可以通过测试装置施加偏压力而弯曲，允许第一触头沿z方向移动以适应第二触点的平面度的变化。

29. 发明授权

US5726075A Method for fabricating microbump interconnect for bare semiconductor dice 失效
标题翻译：用于制造裸半导体晶片的微型块互连的方法
公开(公告)号：US5726075A
公开(公告)日：1998-03-10
申请号：US624991
申请日：1996-03-29
申请人： Warren M. Farnworth , David R. Hembree , Derek Gochnour
发明人： Warren M. Farnworth , David R. Hembree , Derek Gochnour
IPC分类号： H01L21/48 , H01L21/60 , H01L21/28
CPC分类号： H01L24/11 , H01L21/4853 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042
摘要： A method for forming an interconnect for a bare semiconductor is provided. The interconnect includes an insulating film with a pattern of conductors and microbumps adapted to make an electrical connection with contact locations on the die. The insulating film and conductors are mounted to a rigid substrate (e.g., silicon) using an lo elastomeric adhesive. The method includes forming conductive bus bars in electrical communication with the pattern of conductors to provide an electrical path for electroplating the microbumps onto the conductors. Following the electroplating step, the bus bars are severed and separate electrical paths are formed to the conductors. The bus bar can also be used in the completed interconnect to provide a common electrical path to select conductors. The interconnect can be used for testing the die or for providing a permanent electrical connection to the die.
摘要翻译：提供了一种用于形成裸半导体的互连的方法。互连包括绝缘膜，其具有适于与裸片上的接触位置进行电连接的导体和微胶片图案。绝缘膜和导体使用弹性体粘合剂安装到刚性基底（例如硅）上。该方法包括形成与导体图案电连通的导电母线，以提供用于将微胶片电镀到导体上的电路径。在电镀步骤之后，母线被切断，并且与导体形成分开的电路径。母线也可用于完成的互连，以提供选择导体的公共电路。互连可用于测试管芯或提供与管芯的永久电连接。

30. 发明授权

US06263566B1 Flexible semiconductor interconnect fabricated by backslide thinning 有权
标题翻译：通过背面变薄制造的柔性半导体互连
公开(公告)号：US06263566B1
公开(公告)日：2001-07-24
申请号：US09304227
申请日：1999-05-03
申请人： David R. Hembree , Derek Gochnour
发明人： David R. Hembree , Derek Gochnour
IPC分类号： H01R4316
CPC分类号： G01R1/07307 , G01R1/06738 , G01R1/06761 , H01L2224/16237 , H01L2224/8114 , H01R13/24 , Y10T29/49155 , Y10T29/49204 , Y10T29/49208 , Y10T29/49224
摘要： An interconnect for testing semiconductor components includes a thinned substrate, and first contacts on the substrate for electrically engaging second contacts on the components. The interconnect can be configured for use with a testing apparatus for testing discrete components such as dice or chip scale packages, or alternately for use with a testing apparatus for testing wafer sized components, such as wafers, panels and boards. The thinned substrate has a thickness that is substantially less than a thickness of the components being tested. The thinned substrate can flex upon application of a biasing force by the testing apparatus, permitting the first contacts to move in the z-direction to accommodate variations in the planarity of the second contacts. For fabricating the interconnect, the first contacts are formed on the substrate, and then covered with a protective mask. With the mask in place, the substrate can be thinned by grinding, chemical mechanical planarization, or alternately by etching a backside of the substrate. Other process steps such as via formation and backside metallization can also be performed with the protective mask in place. The protective mask can then be removed, and the thinned substrate attached to a rigid substrate, or base, using a compliant polymer layer.
摘要翻译：用于测试半导体部件的互连件包括薄化的衬底，并且衬底上的第一接触件用于电接合部件上的第二接触件。互连可以被配置用于与用于测试分立元件（例如骰子或芯片尺寸封装）的测试设备一起使用，或者替代地与用于测试晶片尺寸的元件（例如晶片，面板和板）的测试设备一起使用。薄化的衬底的厚度实质上小于被测试组件的厚度。减薄的基板可以通过测试装置施加偏压力而弯曲，允许第一触头沿z方向移动以适应第二触点的平面度的变化。为了制造互连，第一触点形成在基板上，然后用保护掩模覆盖。通过掩模就可以通过研磨，化学机械平面化或者通过蚀刻衬底的背面来减薄衬底。其他工艺步骤，例如通孔形成和背面金属化也可以在保护罩就位的情况下进行。然后可以除去保护掩模，并且使用柔顺聚合物层将稀释的基底连接到刚性基底或基底。

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