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    • 23. 发明申请
    • Flash / Phase-Change Memory in Multi-Ring Topology Using Serial-Link Packet Interface
    • 使用串行链路分组接口的多环拓扑中的闪存/相变存储器
    • US20080016269A1
    • 2008-01-17
    • US11773827
    • 2007-07-05
    • David ChowCharles LeeFrank Yu
    • David ChowCharles LeeFrank Yu
    • G06F12/00
    • G06F13/1684G11C13/0004G11C16/102G11C2216/30
    • A multi-ring memory controller sends request packets to multiple rings of serial flash-memory chips. Each of the multiple rings has serial flash-memory chips with serial links in a uni-directional ring. Each serial flash-memory chip has a bypassing transceiver with a device ID checker that bypasses serial packets to a clock re-synchronizer and bypass logic for retransmission to the next device in the ring, or extracts the serial packet to the local device when an ID match occurs. Serial packets pass through all devices in the ring during one round-trip transaction from the controller. The average latency of one round is constant for all devices on the ring, reducing data-dependent performance, since the same packet latency occurs regardless of the data location on the ring. The serial links can be a Peripheral Component Interconnect (PCI) Express bus. Packets have modified-PCI-Express headers that define the packet type and data-payload length.
    • 多环存储器控制器将请求数据包发送到串行闪存芯片的多个环。 多个环中的每个环都具有串行闪存芯片,其具有单向环中的串行链路。 每个串行闪存芯片都具有一个旁路收发器,其中设备ID检查器将串行数据包绕过时钟重新同步器,并且旁路逻辑用于重传到环中的下一个设备,或者当ID为ID时将串行数据包提取给本地设备 匹配发生。 在来自控制器的一次往返事务期间,串行数据包通过环中的所有设备。 由于相同的数据包延迟发生,环路上的所有设备的平均延迟都是恒定的,从而降低了数据相关性能,无论环的数据位置如何。 串行链路可以是外围组件互连(PCI)Express总线。 数据包已经修改了PCI-Express头,定义了数据包类型和数据有效负载长度。
    • 24. 发明申请
    • Two-Level RAM Lookup Table for Block and Page Allocation and Wear-Leveling in Limited-Write Flash-Memories
    • 有限写入闪存中的块和页面分配和磨损均衡的两级RAM查找表
    • US20070204128A1
    • 2007-08-30
    • US11742270
    • 2007-04-30
    • Charles LeeFrank YuDavid Chow
    • Charles LeeFrank YuDavid Chow
    • G06F12/00
    • G06F12/0246G06F2212/1036G06F2212/7211
    • A restrictive multi-level-cell (MLC) flash memory prohibits regressive page-writes. When a regressive page-write is requested, an empty block having a low wear-level count is found, and data from the regressive page-write and data from pages stored in the old block are written to the empty block in page order. The old block is erased and recycled. A two-level look-up table is stored in volatile random-access memory (RAM). A logical page address from a host is divided by a modulo divider to generate a quotient and a remainder. The quotient is a logical block address that indexes a first-level look-up table to find a mapping entry with a physical block address that selects a row in a second-level look-up table. The remainder locates a column in the row in the second-level look-up table. If any page-valid bits above the column pointed to by the remainder are set, the write is regressive.
    • 限制性多电平单元(MLC)闪存禁止回归页面写入。 当请求回归页面写入时,找到具有低磨损级别计数的空块,并且按页顺序将存储在旧块中的页面写入的数据和来自页面的页面的数据写入空块。 旧区被擦除并回收。 两级查找表存储在易失性随机存取存储器(RAM)中。 来自主机的逻辑页地址由模分隔器除以生成商和余数。 商是一个逻辑块地址,其索引第一级查找表以找到具有在二级查找表中选择行的物理块地址的映射条目。 剩余部分在二级查找表中的行中找到一列。 如果设置了剩余部分指向的列之上的任何页面有效位,则写入是回归的。
    • 25. 发明申请
    • Secure-Digital (SD) Flash Card with Auto-Adaptive Protocol and Capacity
    • 具有自适应协议和容量的安全数字(SD)闪存卡
    • US20070168614A1
    • 2007-07-19
    • US11625310
    • 2007-01-20
    • Jianjun LuoChris TsuCharles LeeMing-Shiang Shen
    • Jianjun LuoChris TsuCharles LeeMing-Shiang Shen
    • G06F12/00
    • G06F13/385
    • An adaptable-capacity Secure Digital (SD) card operates as a standard-capacity SD card for a standard-capacity SD 2.0 or 1.x host, and operates as a high-capacity SD card when connected to a high-capacity SD 2.0 host. A 32-bit argument received in a SD bus transaction from the host may be a 32-bit address, which can access 4 G bytes of flash memory in standard-capacity mode. For high-capacity mode, the addressable unit is a 512-byte sector, greatly increasing the addressable memory size. A SD protocol interface on a controller chip performs handshaking with the host to determine the SD version and memory capacity of the host. Host addresses are sent as byte or sector addresses to a flash memory manager on the controller chip, depending on the capacity mode agreed on during the handshaking. Memory areas on the adaptable-capacity SD card for high and standard modes can be separate or overlapping.
    • 适用于容量的安全数字(SD)卡作为标准容量SD 2.0或1.x主机的标准容量SD卡运行,并连接到大容量SD 2.0主机时作为高容量SD卡运行 。 来自主机的SD总线事务中接收到的32位参数可以是32位地址,可以在标准容量模式下访问4 G字节的闪存。 对于高容量模式,可寻址单元是一个512字节的扇区,大大增加了可寻址的存储器大小。 控制器芯片上的SD协议接口与主机执行握手,以确定主机的SD版本和内存容量。 主机地址作为字节或扇区地址发送到控制器芯片上的闪存管理器,这取决于握手期间商定的容量模式。 适用于高容量SD卡的存储区域可以分开或重叠。