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21. 发明授权

US08565030B2 Read boost circuit for memory device 有权
标题翻译：读取存储器件的升压电路
公开(公告)号：US08565030B2
公开(公告)日：2013-10-22
申请号：US13240861
申请日：2011-09-22
申请人： Fady Abouzeid , Sylvain Clerc , Philippe Roche
发明人： Fady Abouzeid , Sylvain Clerc , Philippe Roche
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/065 , G11C11/413
摘要： A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.
摘要翻译：一种读取升压电路，被布置为在读取操作期间升高存储器件的一对互补位线之间的电压差，读取升压电路包括：第一晶体管，其适于由第一晶体管的第一位线一对位线将一对位线的第二位线耦合到第一电源电压; 以及第二晶体管，其直接连接到地，并且适于由第二位线上的电压电平控制，以将第一位线耦合到地。

22. 发明申请

US20110246811A1 METHOD FOR ESTIMATING THE RELIABILITY OF AN ELECTRONIC CIRCUIT, CORRESPONDING COMPUTERIZED SYSTEM AND COMPUTER PROGRAM PRODUCT 审中-公开
标题翻译：评估电子电路可靠性，相关计算机系统和计算机程序产品的可靠性的方法
公开(公告)号：US20110246811A1
公开(公告)日：2011-10-06
申请号：US13074204
申请日：2011-03-29
申请人： Josep Torras Flaquer , Jean-Marc Daveau , Lirida Naviner , Philippe Roche
发明人： Josep Torras Flaquer , Jean-Marc Daveau , Lirida Naviner , Philippe Roche
IPC分类号： G06F11/00
CPC分类号： G06F11/008 , G06F17/50 , G06F2217/10
摘要： The determination of a reliability guideline of an electronic circuit having a nodal network of components including at least one reconvergence path between a correlation source and a sink, involves at the level of each component of the path, a computation of a conditional probability matrix whose conditioning is related to at least one node of the path situated upstream of the component.
摘要翻译：确定具有包括相关源和信宿之间的至少一个再会聚路径的分量节点网络的电子电路的可靠性指南涉及路径的每个分量的水平，条件概率矩阵的计算，其条件概率矩阵的调节与位于组件上游的路径的至少一个节点相关。

23. 发明授权

US07196959B2 Implementation of a multivibrator protected against current or voltage spikes 有权
标题翻译：实现多谐振荡器防止电流或电压尖峰
公开(公告)号：US07196959B2
公开(公告)日：2007-03-27
申请号：US11225887
申请日：2005-09-12
申请人： François Jacquet , Philippe Roche
发明人： François Jacquet , Philippe Roche
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： H03K3/35625 , H03K3/0375 , H03K3/356156
摘要： A multivibrator includes a first data transfer port that receives, as input, multivibrator input data. A first, master, latch cell is connected on the output side of the first transfer port. A second, slave, latch cell is connected thereto through a second data transfer port placed between the first and second latch cells. Each latch cell includes a set of redundant data storage nodes for storing information in at least one pair of complementary nodes and circuitry for restoring information in its initial state, after a current or voltage spike has modified the information in one of the nodes of the said pair, on the basis of the information stored in the other node. The nodes of each pair are implanted opposite one another in a zone of a substrate defining the latch cell.
摘要翻译：多谐振荡器包括接收作为输入的多谐振荡器输入数据的第一数据传送端口。第一个主锁存单元连接在第一个传输端口的输出侧。第二个从锁存单元通过位于第一和第二锁存单元之间的第二数据传送端口连接到其上。每个锁存单元包括一组用于在至少一对互补节点中存储信息的冗余数据存储节点和用于在其初始状态中恢复信息的电路，在电流或电压尖峰已经修改了所述第一个节点中的一个节点中的信息对，基于存储在另一个节点中的信息。每对的节点在限定锁存单元的衬底的区域中彼此相对植入。

24. 发明申请

US20120081978A1 READ BOOST CIRCUIT FOR MEMORY DEVICE 有权
标题翻译：读取存储器件的升压电路
公开(公告)号：US20120081978A1
公开(公告)日：2012-04-05
申请号：US13240861
申请日：2011-09-22
申请人： Fady Abouzeid , Sylvain Clerc , Philippe Roche
发明人： Fady Abouzeid , Sylvain Clerc , Philippe Roche
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/065 , G11C11/413
摘要： A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.
摘要翻译：一种读取升压电路，被布置为在读取操作期间升高存储器件的一对互补位线之间的电压差，读取升压电路包括：第一晶体管，其适于由第一晶体管的第一位线一对位线将一对位线的第二位线耦合到第一电源电压; 以及第二晶体管，其直接连接到地，并且适于由第二位线上的电压电平控制，以将第一位线耦合到地。

25. 发明授权

US07535743B2 SRAM memory cell protected against current or voltage spikes 有权
标题翻译： SRAM存储单元保护电流或电压尖峰
公开(公告)号：US07535743B2
公开(公告)日：2009-05-19
申请号：US11225876
申请日：2005-09-12
申请人： Philippe Roche , François Jacquet
发明人： Philippe Roche , François Jacquet
IPC分类号： G11C5/06
CPC分类号： G11C11/4125 , G11C5/005
摘要： A memory cell is protected against current or voltage spikes. The cell includes a group of redundant data storage nodes for the storage of information in at least one pair of complementary nodes. The cell further includes circuitry for restoring information to its initial state following a current or voltage spike which modifies the information in one of the nodes of the pair using the information stored in the other node. The data storage nodes of each pair in the cell are implanted on opposite sides of an opposite conductivity type well from one another within a region of a substrate defining the boundaries of the memory cell.
摘要翻译：存储器单元被保护以防止电流或电压尖峰。小区包括用于在至少一对互补节点中存储信息的一组冗余数据存储节点。小区还包括用于在当前或电压尖峰之后将信息恢复到其初始状态的电路，其使用存储在另一节点中的信息来修改对中的一个节点中的信息。单元中每对的数据存储节点在限定存储单元的边界的衬底的区域内相互注入相对导电类型的相对侧。

26. 发明授权

US07292482B2 Multivibrator protected against current or voltage spikes 有权
标题翻译：多谐振荡器可防止电流或电压尖峰
公开(公告)号：US07292482B2
公开(公告)日：2007-11-06
申请号：US11225848
申请日：2005-09-12
申请人： Philippe Roche , François Jacquet
发明人： Philippe Roche , François Jacquet
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： H03K3/35625 , H03K3/013 , H03K3/0375 , H03K3/356156
摘要： A multivibrator circuit includes a first data transfer port that receives, as input, multivibrator input data, a first, master, latch cell connected on the output side of the first transfer port, a second, slave, latch cell, and a second data transfer port placed between the first and second latch cells, each latch cell comprising a set of redundant data storage nodes. The transfer ports each include circuitry for writing data separately into each storage node.
摘要翻译：多谐振荡器电路包括第一数据传输端口，其接收多谐振荡器输入数据作为输入，连接在第一传输端口的输出侧上的第一，主，锁存单元，第二从机，锁存单元和第二数据传输端口位于第一和第二锁存单元之间，每个锁存单元包括一组冗余数据存储节点。传送端口各自包括用于将数据分别写入每个存储节点的电路。

27. 发明授权

US06765405B2 Protection circuit against voltage or current spikes, and clock circuit using a protection circuit of this kind 失效
标题翻译：防止电压或电流尖峰的保护电路，以及使用这种保护电路的时钟电路
公开(公告)号：US06765405B2
公开(公告)日：2004-07-20
申请号：US10191089
申请日：2002-07-09
申请人： Jean-Francois Hugues , Philippe Roche , Richard Ferrant
发明人： Jean-Francois Hugues , Philippe Roche , Richard Ferrant
IPC分类号： H03K1716
CPC分类号： H03K19/00338 , H03K19/0075
摘要： Disclosed are protection circuitry, and methods of operating the same, for use with clock circuits associated with integrated circuits (ICs). According to one exemplary embodiment, the protection circuitry is operable to generate at least two intermediate clock signals as a function of a received clock signal, and process the at least two intermediate clock signals to (i) cause an output of the protection circuitry to enter a high-impedance state when the at least two intermediate clock signals are different, and (ii) generate a resultant clock signal at the output of the protection circuitry equal to the received clock signal when the at least two intermediate clock signals are identical.
摘要翻译：公开了用于与集成电路（IC）相关的时钟电路使用的保护电路及其操作方法。根据一个示例性实施例，保护电路可操作以产生作为接收到的时钟信号的函数的至少两个中间时钟信号，并处理该至少两个中间时钟信号以使（i）使保护电路的输出进入当所述至少两个中间时钟信号不同时，高阻抗状态;以及（ii）当所述至少两个中间时钟信号相同时，在所述保护电路的输出处产生等于接收到的时钟信号的合成时钟信号。

28. 发明授权

US06630719B2 Hardened MOS transistors 有权
标题翻译：硬化MOS晶体管
公开(公告)号：US06630719B2
公开(公告)日：2003-10-07
申请号：US09731266
申请日：2000-12-06
申请人： Philippe Roche
发明人： Philippe Roche
IPC分类号： H01L2976
CPC分类号： H01L27/11 , H01L27/0255
摘要： A lateral MOS transistor including a gate and drain and source regions of a first conductivity type formed in a substrate of a second conductivity type connected to a first power supply, wherein a doped buried layer of the first conductivity type extends under said drain region and under a portion of the gate, the buried layer being connected to the gate via a one-way connection.
摘要翻译：一种横向MOS晶体管，包括栅极和漏极以及形成在与第一电源连接的第二导电类型的衬底中的第一导电类型的源极区域，其中第一导电类型的掺杂掩埋层在所述漏极区域下方延伸，栅极的一部分，埋层通过单向连接连接到栅极。

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