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21. 发明申请

US20100169559A1 Removable Mother/Daughter Peripheral Card 审中-公开
标题翻译：可拆卸的母亲/女儿外围卡
公开(公告)号：US20100169559A1
公开(公告)日：2010-07-01
申请号：US12723491
申请日：2010-03-12
申请人： Eliyahou Harari , Daniel C. Guterman , Robert F. Wallace
发明人： Eliyahou Harari , Daniel C. Guterman , Robert F. Wallace
IPC分类号： G06F13/00 , G06F12/02
CPC分类号： G06F13/4068 , G06K19/07741 , H05K5/0265 , H05K5/0282
摘要： A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.
摘要翻译：具有个人计算机（“PC”）卡形状因子并且可拆卸地耦合到主机系统外部的外围卡进一步被划分为母卡部分和子卡部分。子卡可拆卸地耦合到母卡。在优选实施例中，低成本闪存“软盘”是通过仅包含快闪EEPROM芯片的子卡并由驻留在母卡上的存储器控制器来控制的。本发明的其它方面包括：母卡上的综合控制器，其能够控制可连接到母卡的子卡上的预定义的一组外围设备; 将一些主机驻地硬件重定位到母卡以允许最小的主机系统; 可容纳多张子卡的母卡; 子卡也直接与具有嵌入式控制器的主机操作; 携带编码数据的子卡和用于解码的信息; 和具有安全功能的子卡。

22. 发明申请

US20100039859A1 System and Method for Programming Cells in Non-Volatile Integrated Memory Devices 有权
标题翻译：用于在非易失性集成存储器件中编程单元的系统和方法
公开(公告)号：US20100039859A1
公开(公告)日：2010-02-18
申请号：US12604904
申请日：2009-10-23
申请人： Nima Mokhlesi , Daniel C. Guterman
发明人： Nima Mokhlesi , Daniel C. Guterman
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C11/5671 , G11C16/3459 , G11C16/3468 , G11C16/3481 , G11C2211/5621
摘要： A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated. According to another aspect, during a program operation the current limit allowed for a cell depends upon the target state to which it is to be programmed.
摘要翻译：提出了一种用于在非易失性集成存储器件中快速高效地编程难编程存储元件的系统和方法。多个存储元件同时进行编程处理，其中流过存储元件的电流限于第一级。随着这些存储元件的一部分达到规定的状态，它们被从被编程的单元组移除，并且提高了继续编程的元件上的电流限制。这些难以编程的单元格中的当前级别可以提高到第二个，更高的限制或不受管制。根据另一方面，在程序操作期间，允许单元的电流限制取决于要被编程的目标状态。

23. 发明授权

US07633807B2 Behavior based programming of non-volatile memory 有权
标题翻译：非易失性存储器的基于行为的编程
公开(公告)号：US07633807B2
公开(公告)日：2009-12-15
申请号：US11624052
申请日：2007-01-17
申请人： Jian Chen , Jeffrey W. Lutze , Yan Li , Daniel C. Guterman , Tomoharu Tanaka
发明人： Jian Chen , Jeffrey W. Lutze , Yan Li , Daniel C. Guterman , Tomoharu Tanaka
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3459
摘要： The process for programming a set of memory cells is improved by adapting the programming process based on behavior of the memory cells. For example, a set of program pulses is applied to the word line for a set of flash memory cells. A determination is made as to which memory cells are easier to program and which memory cells are harder to program. Bit line voltages (or other parameters) can be adjusted based on the determination of which memory cells are easier to program and which memory cells are harder to program. The programming process will then continue with the adjusted bit line voltages (or other parameters).
摘要翻译：通过基于存储器单元的行为调整编程过程来改进用于对一组存储器单元进行编程的过程。例如，一组编程脉冲被施加到一组闪存单元的字线。确定哪些存储器单元更容易编程，哪些存储器单元难以编程。可以基于确定哪些存储器单元更容易编程以及哪些存储器单元难以编程来调整位线电压（或其他参数）。然后，编程过程将继续调整的位线电压（或其他参数）。

24. 发明授权

US07457162B2 Multi-state memory 失效
公开(公告)号：US07457162B2
公开(公告)日：2008-11-25
申请号：US11868225
申请日：2007-10-05
申请人： Daniel C. Guterman , Yupin Kawing Fong
发明人： Daniel C. Guterman , Yupin Kawing Fong
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C27/005 , G11C29/00 , G11C29/76 , G11C2211/5634 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

25. 发明授权

US07453730B2 Charge packet metering for coarse/fine programming of non-volatile memory 有权
公开(公告)号：US07453730B2
公开(公告)日：2008-11-18
申请号：US11429769
申请日：2006-05-08
申请人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C2211/5621 , G11C2211/5624
摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

26. 发明授权

US07449746B2 EEPROM with split gate source side injection 失效
标题翻译：带分流栅源的EEPROM注入
公开(公告)号：US07449746B2
公开(公告)日：2008-11-11
申请号：US11278778
申请日：2006-04-05
申请人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
发明人： Daniel C. Guterman , Gheorghe Samachisa , Yupin Kawing Fong , Eliyahou Harari
IPC分类号： H01L29/94
CPC分类号： H01L27/11521 , G11C16/0425 , G11C16/0458 , G11C16/0491 , H01L27/115 , H01L29/7881
摘要： Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.
摘要翻译：新型存储单元利用源侧注入，允许非常小的编程电流。如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于后续写操作。在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。如果所有待编程的单元都已被正确编程，则位线电流将基本为零。如果检测到位线电流，则对扇区的所有单元执行另一写操作，并且执行另一验证操作。重复此写/验证过程，直到验证成功，如检测到或基本为零，位线电流。

27. 发明授权

US07443723B2 Multi-state memory 有权
公开(公告)号：US07443723B2
公开(公告)日：2008-10-28
申请号：US10809572
申请日：2004-03-24
申请人： Daniel C. Guterman , Yupin Kawing Fong
发明人： Daniel C. Guterman , Yupin Kawing Fong
IPC分类号： G11C16/04
CPC分类号： H01L27/115 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C27/005 , G11C29/00 , G11C29/76 , G11C2211/5634 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

28. 发明授权

US07414887B2 Variable current sinking for coarse/fine programming of non-volatile memory 有权
标题翻译：用于非易失性存储器粗/精编程的可变电流吸收
公开(公告)号：US07414887B2
公开(公告)日：2008-08-19
申请号：US11280716
申请日：2005-11-16
申请人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
发明人： Daniel C. Guterman , Nima Mokhlesi , Yupin Fong
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3481 , G11C27/005
摘要： A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.
摘要翻译：通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

29. 发明授权

US07307884B2 Concurrent programming of non-volatile memory 有权
标题翻译：并发编程非易失性存储器
公开(公告)号：US07307884B2
公开(公告)日：2007-12-11
申请号：US10868147
申请日：2004-06-15
申请人： Daniel C. Guterman
发明人： Daniel C. Guterman
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/10
摘要： One embodiment of the present invention includes applying a first value to a bit line, boosting word lines associated with the bit line and a common selection line to create a first condition based on the first value, and cutting off a boundary non-volatile storage element associated with the common selection line to maintain the first condition for a particular non-volatile storage element associated with the bit line and common selection line. A second value is applied to the bit line and at least a subset of the word lines are boosted to create a second condition for a different non-volatile storage element associated with the bit line and common selection line. The second condition is based on the second value. The first condition and the second condition overlap in time. Both non-volatile storage elements are programmed concurrently, based on their associated conditions.
摘要翻译：本发明的一个实施例包括将第一值应用于位线，升高与位线相关联的字线和公共选择线，以基于第一值创建第一条件，并切断边界非易失性存储元件与公共选择线相关联，以维持与位线和公共选择线相关联的特定非易失性存储元件的第一条件。将第二值应用于位线，并且提高字线的至少一个子集以为与位线和公共选择线相关联的不同非易失性存储元件创建第二条件。第二个条件是基于第二个值。第一个条件和第二个条件在时间上重叠。这两个非易失性存储元件都是根据其相关条件同时编程的。

30. 发明授权

US07289360B2 Multi-state memory 有权
公开(公告)号：US07289360B2
公开(公告)日：2007-10-30
申请号：US11330923
申请日：2006-01-11
申请人： Daniel C. Guterman , Yupin Kawing Fong
发明人： Daniel C. Guterman , Yupin Kawing Fong
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/28 , G11C16/3418 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C27/005 , G11C29/00 , G11C29/76 , G11C2211/5634 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

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