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21. 发明授权

US6139697A Low temperature integrated via and trench fill process and apparatus 失效
标题翻译：低温集成通孔和沟槽填充工艺和设备
公开(公告)号：US6139697A
公开(公告)日：2000-10-31
申请号：US792292
申请日：1997-01-31
申请人： Liang-Yuh Chen , Roderick Craig Mosely , Fusen Chen , Rong Tao , Ted Guo
发明人： Liang-Yuh Chen , Roderick Craig Mosely , Fusen Chen , Rong Tao , Ted Guo
IPC分类号： H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , C23C14/34
CPC分类号： H01L21/76877
摘要： The present invention relates generally to an improved process for providing complete via fill on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer, such as CVD Al or CVD Cu, is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD Cu. Next, a PVD Cu is deposited onto the previously formed CVD Cu layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD Cu layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Cu layer. The via fill process of the present invention is also successful with air-exposure between the CVD Cu and PVD Cu steps.
摘要翻译：本发明一般涉及在衬底上提供完整的通孔填充物和金属层的平坦化以在半微米应用中形成连续的无空隙触点或通孔的改进方法。在本发明的一个方面中，将耐火层沉积在具有高比例接触或在其上形成的通孔的基底上。然后将CVD金属层（例如CVD Al或CVD Cu）在低温下沉积到耐火层上，以提供用于PVD Cu的保形润湿层。接下来，在低于金属的熔点温度的温度下，将PVD Cu沉积在先前形成的CVD Cu层上。所得到的CVD / PVD Cu层基本上无空隙。金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，就会发生通孔和触点的金属化，而不会在其上形成氧化物层 CVD Cu层。本发明的通孔填充方法也可以在CVD Cu和PVD Cu步骤之间的空气曝光成功。

22. 发明授权

US6001420A Semi-selective chemical vapor deposition 失效
标题翻译：半选择性化学气相沉积
公开(公告)号：US6001420A
公开(公告)日：1999-12-14
申请号：US718656
申请日：1996-09-23
申请人： Roderick Craig Mosely , Liang-Yuh Chen , Ted Guo
发明人： Roderick Craig Mosely , Liang-Yuh Chen , Ted Guo
IPC分类号： C23C16/06 , H01L21/28 , H01L21/285 , H01L21/768 , B05D1/36 , C23C16/00
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76876 , H01L21/76877 , H01L2221/1089 , Y10S977/891
摘要： The present invention is a method for semi-selectively depositing a material on a substrate by chemical vapor deposition to form continuous, void-free contact holes or vias in sub-half micron applications. An insulating layer is preferentially deposited on the field of a substrate to delay or inhibit nucleation of metal on the field. A CVD metal is then deposited onto the substrate and grows selectively in the contact hole or via where a barrier layer serves as a nucleation layer. The process is preferably carried out in a multi-chamber system that includes both PVD and CVD processing chambers so that once the substrate is introduced into a vacuum environment, the filling of contact holes and vias occurs without the formation of an oxide layer on a patterned substrate.
摘要翻译：本发明是通过化学气相沉积在衬底上半选择性沉积材料以在半微米应用中形成连续的无空隙接触孔或通孔的方法。绝缘层优先沉积在衬底的场上以延迟或抑制场上金属的成核。然后将CVD金属沉积到衬底上并选择性地生长在接触孔中，或通过其中阻挡层用作成核层。该方法优选在包括PVD和CVD处理室的多室系统中进行，使得一旦将基底引入真空环境中，接触孔和通孔的填充发生，而在图案上没有形成氧化物层基质。

23. 发明授权

US5989623A Dual damascene metallization 失效
标题翻译：双镶嵌金属化
公开(公告)号：US5989623A
公开(公告)日：1999-11-23
申请号：US914521
申请日：1997-08-19
申请人： Liang-Yuh Chen , Rong Tao , Ted Guo , Roderick Craig Mosely
发明人： Liang-Yuh Chen , Rong Tao , Ted Guo , Roderick Craig Mosely
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , B05D5/12
CPC分类号： H01L21/76843 , H01L21/76831 , H01L21/76862 , H01L21/76876 , H01L21/76877 , H01L21/76807
摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.
摘要翻译：本发明通常提供用于形成高度集成的互连件的金属化工艺。更具体地，本发明提供了一种双镶嵌互连模块，其包含沉积在包含双镶嵌通孔和线定义的电介质层的所有暴露表面上的阻挡层。在平坦化之前，使用两种或更多种沉积方法在阻挡层上沉积导电金属以填充通孔和导线的定义。本发明提供了具有比铝更低的电阻率（更大的导电性）和更大的电迁移电阻的铜线，铜线和周围介电材料之间的阻挡层，无空隙的半微米选择性CVD Al通过插塞的优点，并减少了实现这种集成的流程步骤。

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