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21. 发明授权

US6118304A Method and apparatus for logic synchronization 有权
标题翻译：用于逻辑同步的方法和装置
公开(公告)号：US6118304A
公开(公告)日：2000-09-12
申请号：US179330
申请日：1998-10-27
申请人： Terence M. Potter , James S. Blomgren , Anthony M. Petro , Stephen C. Horne
发明人： Terence M. Potter , James S. Blomgren , Anthony M. Petro , Stephen C. Horne
IPC分类号： G06F1/08 , G06F5/01 , G06F7/02 , G06F7/49 , G06F7/50 , G06F7/544 , G06F17/50 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/096 , H03K19/21
CPC分类号： G06F7/026 , G06F1/08 , G06F17/5045 , G06F5/015 , G06F7/02 , G06F7/49 , G06F7/5443 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/096 , H03K19/0963 , H03K19/215 , G06F2207/3824 , G06F7/483 , G06F7/508 , G11C7/1006
摘要： The present invention comprises a plurality of clock signals with an approximately 50% duty cycle and overlapping phases. The phases of the plurality of clocks are such that the phase of an individual clock signal overlaps the phase of an earlier clock signal by an amount equal to the overlap of the phase of the next clock signal. The present invention further comprises a plurality of clocked precharge (CP) logic gates coupled in series. An individual CP logic gate couples to an individual clock signal though the CP logic gate's evaluate device. For the data flow through the individual CP logic gate, the logic gate receives its data input from an earlier CP logic gate in the series and passes to the next CP logic gate in the series. The earlier CP logic gate couples to an earlier phase clock signal, and the next CP logic gate couples to the next phase clock signal. The present invention additionally provides that a logic gate may only feed another logic circuit in a feed back loop or a feed forward loop that uses the next phase clock signal.
摘要翻译：本发明包括具有约50％占空比和重叠相位的多个时钟信号。多个时钟的相位使得各个时钟信号的相位与较早时钟信号的相位重叠等于下一个时钟信号的相位重叠的量。本发明还包括串联耦合的多个时钟预充电（CP）逻辑门。单个CP逻辑门通过CP逻辑门的评估设备耦合到单独的时钟信号。对于通过单个CP逻辑门的数据流，逻辑门从串联的较早的CP逻辑门接收其数据输入，并传递到序列中的下一个CP逻辑门。较早的CP逻辑门耦合到较早的相位时钟信号，下一个CP逻辑门耦合到下一个相位时钟信号。本发明另外提供了一种逻辑门仅可以在使用下一个相位时钟信号的反馈回路或前馈回路中馈送另一个逻辑电路。

22. 发明授权

US6115294A Method and apparatus for multi-bit register cell 有权
标题翻译：多位寄存器单元的方法和装置
公开(公告)号：US6115294A
公开(公告)日：2000-09-05
申请号：US291659
申请日：1999-04-14
申请人： James S. Blomgren , Terence M. Potter , Michael R. Seningen , Stephen C. Horne
发明人： James S. Blomgren , Terence M. Potter , Michael R. Seningen , Stephen C. Horne
IPC分类号： G06F1/08 , G06F5/01 , G06F7/02 , G06F7/49 , G06F7/50 , G06F7/544 , G06F17/50 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/096 , H03K19/21 , G11C7/00
CPC分类号： G06F7/5443 , G06F1/08 , G06F17/5045 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/49 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215 , G06F2207/3824 , G06F7/483 , G06F7/508 , G11C7/1006
摘要： The present invention is a method and apparatus for a register cell that is configured to store more than one bit of information. The cell includes a multiplexer that is configurable to select various inputs when the multiplexer is in various states. The multiplexer is configurable to select a first input when the multiplexer is in a first state, and to select a second input when the multiplexer is in a second state. The multiplexer is further configured to provide multi-bit storage data, the first input being configured to receive multi-bit data from outside the cell. An output element, such as a second multiplexer, is configured to receive a word enable. The output of the first multiplexer is delayed in a delay element, and is provided as one of the inputs to the first multiplexer.
摘要翻译：本发明是一种用于寄存器单元的方法和装置，其被配置为存储多于一位的信息。该单元包括多路复用器，其可配置为当多路复用器处于不同状态时选择各种输入。多路复用器可配置为当多路复用器处于第一状态时选择第一输入，并且当多路复用器处于第二状态时选择第二输入。复用器还被配置为提供多位存储数据，第一输入被配置为从单元外部接收多位数据。诸如第二多路复用器的输出元件被配置为接收字使能。第一多路复用器的输出在延迟元件中延迟，并且被提供为第一多路复用器的输入之一。

23. 发明授权

US6069836A Method and apparatus for a RAM circuit having N-nary word line generation 有权
标题翻译：具有N字字线生成的RAM电路的方法和装置
公开(公告)号：US6069836A
公开(公告)日：2000-05-30
申请号：US150162
申请日：1998-09-09
申请人： Stephen C. Horne , Michael R. Seningen , James S. Blomgren
发明人： Stephen C. Horne , Michael R. Seningen , James S. Blomgren
IPC分类号： G06F1/08 , G06F17/50 , G11C8/10 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/00 , H03K19/003 , H03K19/096 , G11C8/00
CPC分类号： G06F1/08 , G06F17/5045 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , G11C8/10 , G11C8/18 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0963 , G11C7/1006
摘要： A memory device having a sense trigger coupled to receive an address when available, and to assert a sense trigger signal to the sense trigger when the sense trigger receives the address. The memory device also has an N-nary, or 1-of-N, input logic gate that provides additional assurance that no more than one word line is asserted when an address is decoded. The memory device also has an N-nary, or 1-of-N, output driver logic gate that provides an output signal directly useful for providing to another (N-nary) 1-of-N logic gate.
摘要翻译：具有感测触发器的存储器件，其在耦合到可用时接收地址，并且当感测触发器接收到地址时，将感测触发信号置于感测触发器。存储器件还具有N / N或N输入逻辑门，其提供额外的保证，即当解码地址时不超过一个字线被断言。存储器件还具有N输出或1-N输出驱动器逻辑门，其提供直接用于提供给另一（N-Nary）1-N逻辑门的输出信号。

24. 发明授权

US6069497A Method and apparatus for a N-nary logic circuit using 1 of N signals 失效
标题翻译：使用1个N信号的N-Nary逻辑电路的方法和装置
公开(公告)号：US6069497A
公开(公告)日：2000-05-30
申请号：US19244
申请日：1998-02-05
申请人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M. Petro
发明人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M. Petro
IPC分类号： G06F1/08 , G06F5/01 , G06F7/02 , G06F7/49 , G06F7/50 , G06F7/544 , G06F17/50 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/096 , H03K19/21 , H03K19/094 , H03K19/20
CPC分类号： G06F1/08 , G06F17/5045 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/49 , G06F7/5443 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215 , G06F2207/3824 , G06F7/483 , G06F7/508 , G11C7/1006
摘要： The present invention is a method and apparatus for a N-nary logic circuit that comprises a logic tree circuit that couples to a first set of input logic paths, a second set of input logic paths, and a set of output logic paths, which all use 1 of N signals where one and only one of the N logic paths is active during an evaluation cycle. The preferred embodiment of the present invention uses 1 of 4 signals, while other embodiments of present invention include 1 of 2 signals, 1 of 3 signals, 1 of 8 encoding, and the general embodiment of the 1 of N signals. The logic tree circuit evaluates a given function that includes, for example, an AND/NAND function, an OR/NOR function, or an XOR/Equivalence function. The logic tree circuit uses a single, shared logic tree with multiple evaluation paths for evaluating the function of the logic circuit.
摘要翻译：本发明是一种用于N-Nary逻辑电路的方法和装置，其包括耦合到第一组输入逻辑路径的逻辑树电路，第二组输入逻辑路径和一组输出逻辑路径，所有这些都是使用N个信号中的1个，其中N个逻辑路径中的一个且仅一个在评估周期期间是活动的。本发明的优选实施例使用4个信号中的1个，而本发明的其它实施例包括2个信号中的1个，3个信号中的1个，8个编码中的1个，以及N个信号的1个的一般实施例。逻辑树电路评估包括例如AND / NAND功能，OR / NOR功能或XOR /等效函数的给定功能。逻辑树电路使用具有多个评估路径的单个共享逻辑树来评估逻辑电路的功能。

25. 发明授权

US6066965A Method and apparatus for a N-nary logic circuit using 1 of 4 signals 失效
标题翻译：使用4个信号中的1个的N-Nary逻辑电路的方法和装置
公开(公告)号：US6066965A
公开(公告)日：2000-05-23
申请号：US19355
申请日：1998-02-05
申请人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M. Petro
发明人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M. Petro
IPC分类号： G06F1/08 , G06F17/50 , G11C8/10 , G11C8/18 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/096 , H03K19/21 , H03K19/20
CPC分类号： G06F1/08 , G06F17/5045 , G11C11/419 , G11C11/56 , G11C19/00 , G11C8/10 , G11C8/18 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215 , G11C7/1006 , G11C8/00
摘要： The present invention is a method and apparatus for a N-nary logic circuit that comprises a logic tree circuit that couples to a first set of input logic paths, a second set of input logic paths, and a set of output logic paths, which all use 1 of N signals where one and only one of the N logic paths is active during an evaluation cycle. The preferred embodiment of the present invention uses 1 of 4 signals, while other embodiments of present invention include 1 of 2 signals, 1 of 3 signals, 1 of 8 encoding, and the general embodiment of the 1 of N signals. The logic tree circuit evaluates a given function that includes, for example, an AND/NAND function, an OR/NOR function, or an XOR/Equivalence function. The logic tree circuit uses a single, shared logic tree with multiple evaluation paths for evaluating the function of the logic circuit.
摘要翻译：本发明是一种用于N-Nary逻辑电路的方法和装置，其包括耦合到第一组输入逻辑路径的逻辑树电路，第二组输入逻辑路径和一组输出逻辑路径，所有这些都是使用N个信号中的1个，其中N个逻辑路径中的一个且仅一个在评估周期期间是活动的。本发明的优选实施例使用4个信号中的1个，而本发明的其它实施例包括2个信号中的1个，3个信号中的1个，8个编码中的1个，以及N个信号的1个的一般实施例。逻辑树电路评估包括例如AND / NAND功能，OR / NOR功能或XOR /等效函数的给定功能。逻辑树电路使用具有多个评估路径的单个共享逻辑树来评估逻辑电路的功能。

26. 发明授权

US5751173A Variable strength clock signal driver and method of manufacturing the same 失效
公开(公告)号：US5751173A
公开(公告)日：1998-05-12
申请号：US517477
申请日：1995-08-21
申请人： Scott H. R. McMahon , James Michael Buchanan , Stephen C. Horne
发明人： Scott H. R. McMahon , James Michael Buchanan , Stephen C. Horne
IPC分类号： H03K17/12 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K5/12
CPC分类号： H03K19/00361 , H03K19/018585
摘要： A variable strength clock signal driver circuit and method of manufacturing the same are provided that accommodate either full or reduced drive strength of a generated clock signal. The clock driver circuit includes a package bonding option to select the desired strength of drive. Thus, the clock driver circuit may be operated at either fast or slow clock frequencies as determined by the system requirements. As a result, both high performance, high drive versions and low cost, low drive versions of a digital circuit such as a microprocessor may be provided that differ only in package bonding. The same set of masks may be used to produce either version of the circuit, thus permitting greater manufacturing flexibility and reducing cost. Furthermore, electromagnetic interference may be reduced by selecting the low drive strength option for cost sensitive applications.

27. 发明授权

US5444406A Self-adjusting variable drive strength buffer circuit and method for controlling the drive strength of a buffer circuit 失效
标题翻译：自调节可变驱动强度缓冲电路及控制缓冲电路驱动强度的方法
公开(公告)号：US5444406A
公开(公告)日：1995-08-22
申请号：US14955
申请日：1993-02-08
申请人： Stephen C. Horne
发明人： Stephen C. Horne
IPC分类号： G06F1/04 , G11C11/407 , H03K5/13 , H03K19/003 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018585 , H03K19/00384 , H03K5/131
摘要： A variable drive strength buffer circuit is provided that automatically adjusts its associated drive strength to compensate for variations in manufacturing parameters, environmental conditions and operating conditions. As a result, electromagnetic interference, power supply noise, edge rates and ringing may be reduced. The self-adjusting variable drive buffer circuit may be fabricated on an integrated circuit and includes a speed detector unit that measures the relative speed of the integrated circuit. In one embodiment, a self-adjusting variable drive strength buffer circuit includes a circuit speed detector unit having a delay chain consisting of a plurality of variable delay elements. When the delay chain length is matched to the period of an input clock, the length of the chain is an accurate measure of the relative "speed" of the transistors making up the delay chain and therefore of the other transistors on the integrated circuit chip. The length of the delay chain is encoded into a vector (one or more digital bits of information) that controls the amount of drive that is provided in the variable drive buffer circuit. More drive is provided if the transistors on the chip are relatively slow and less drive is provided if the transistors are relatively fast.
摘要翻译：提供了可变驱动强度缓冲电路，其自动调整其相关联的驱动强度以补偿制造参数，环境条件和操作条件的变化。因此，可能会降低电磁干扰，电源噪声，边沿速率和振铃。自调节可变驱动缓冲电路可以在集成电路上制造，并且包括测量集成电路的相对速度的速度检测器单元。在一个实施例中，自调节可变驱动强度缓冲电路包括具有由多个可变延迟元件组成的延迟链的电路速度检测器单元。当延迟链长度与输入时钟的周期匹配时，链的长度是组成延迟链的晶体管和集成电路芯片上的其他晶体管的相对“速度”的精确测量。延迟链的长度被编码为控制可变驱动缓冲电路中提供的驱动量的向量（一个或多个数字信息位）。如果芯片上的晶体管相对较慢，则提供更多的驱动，如果晶体管相对较快，则提供较少的驱动。

28. 发明申请

US20130111130A1 MEMORY INCLUDING A REDUCED LEAKAGE WORDLINE DRIVER 有权
标题翻译：内存包括减少字幕驱动程序
公开(公告)号：US20130111130A1
公开(公告)日：2013-05-02
申请号：US13286351
申请日：2011-11-01
申请人： Edward M. McCombs , Stephen C. Horne , Alexander E. Runas , Daniel C. Chow
发明人： Edward M. McCombs , Stephen C. Horne , Alexander E. Runas , Daniel C. Chow
IPC分类号： G11C5/14 , G06F12/08
CPC分类号： G11C8/08
摘要： A memory includes a wordline driver having reduced leakage. The memory includes a storage array coupled to a first voltage supply, and a number of wordline driver units each including a driver inverter. During a low power mode, the voltage of the voltage supply coupled to the wordline circuit is reduced or removed, while the voltage of the voltage supply coupled to the storage array is kept at least at a retention voltage. In addition a p-type transistor is coupled between the array voltage supply and an input to the wordline driver inverter, thereby keeping the output of the wordline driver inverter at a low logic level to prevent inadvertent wordline firing.
摘要翻译：存储器包括具有减少的泄漏的字线驱动器。存储器包括耦合到第一电压源的存储阵列以及包括驱动器反相器的多个字线驱动器单元。在低功率模式期间，耦合到字线电路的电压源的电压被减小或去除，而耦合到存储阵列的电压源的电压至少保持在保持电压。此外，p型晶体管耦合在阵列电压源和字线驱动器反相器的输入之间，从而将字线驱动器反相器的输出保持在低逻辑电平以防止意外的字线触发。

29. 发明授权

US06288589B1 Method and apparatus for generating clock signals 有权
标题翻译：用于产生时钟信号的方法和装置
公开(公告)号：US06288589B1
公开(公告)日：2001-09-11
申请号：US09179745
申请日：1998-10-27
申请人： Terence M. Potter , James S. Blomgren , Anthony M. Petro , Stephen C. Horne
发明人： Terence M. Potter , James S. Blomgren , Anthony M. Petro , Stephen C. Horne
IPC分类号： G06F104
CPC分类号： G06F7/026 , G06F1/08 , G06F5/015 , G06F7/02 , G06F7/483 , G06F7/49 , G06F7/508 , G06F7/5443 , G06F17/5045 , G06F2207/3824 , G11C7/1006 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/096 , H03K19/0963 , H03K19/215
摘要： The present invention comprises a master global clock distributed in a low-skew manner over a relevant clock domain area coupled with a plurality of locally generated clocks in said clock domain area. The plurality of locally generated clocks are tuned to allow for skew and jitter tolerance. The present invention further comprises embodiments with 3, 4, 5, and 6 locally generated clocks.
摘要翻译：本发明包括一个主时钟全局时钟，该主时钟在与时钟域区域中的多个本地生成的时钟耦合的相关时钟域区域上以低歪斜方式分布。调整多个本地生成的时钟以允许偏斜和抖动容限。本发明还包括具有3,4,5和6本地生成的时钟的实施例。

30. 发明授权

US06268746B1 Method and apparatus for logic synchronization 有权
标题翻译：用于逻辑同步的方法和装置
公开(公告)号：US06268746B1
公开(公告)日：2001-07-31
申请号：US09586638
申请日：2000-06-05
申请人： Terence M. Potter , James S. Blomgren , Anthony M. Petro , Stephen C. Horne
发明人： Terence M. Potter , James S. Blomgren , Anthony M. Petro , Stephen C. Horne
IPC分类号： H03K19096
CPC分类号： G06F7/026 , G06F1/08 , G06F5/015 , G06F7/02 , G06F7/483 , G06F7/49 , G06F7/508 , G06F7/5443 , G06F17/5045 , G06F2207/3824 , G11C7/1006 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/096 , H03K19/0963 , H03K19/215
摘要： The present invention is a method and apparatus that synchronizes logic in an integrated circuit (IC). The present invention discloses a global clock signal with a global phase and an approximately 50% duty cycle. Additionally, the present invention discloses a first local clock signal with a first phase and an approximately 50% duty cycle that couples to a first dynamic logic gate where the first local clock signal is generated from the global clock signal. One or more intermediate local clock signals with one or more intermediate phases are generated from the global clock signal where each intermediate local clock signal has an approximately 50% duty cycle that couples to one or more intermediate dynamic logic gates. An end local clock signal with an end phase and an approximately 50% dutycycle that is also generated from the global clock signal and that couples to an end dynamic logic gate. The phase of an individual local clock signal overlaps an earlier phase local clock signal by an amount approximately equal to the overlap of the phase of the next individual local clock signal. The first dynamic logic gate, the intermediate dynamic logic gate(s), and the last dynamic logic gates couple such that an individual dynamic logic gate with an individual local clock signal and phase may only provide a signal to the next individual dynamic logic gate that uses a next phase local clock signal where the gates may couple together in series, in a feed back loop, or a feed forward loop.
摘要翻译：本发明是一种使集成电路（IC）中的逻辑同步的方法和装置。本发明公开了具有全局相位和约50％占空比的全局时钟信号。此外，本发明公开了具有第一相位和约50％占空比的第一本地时钟信号，其耦合到第一动态逻辑门，其中从全局时钟信号产生第一本地时钟信号。从全局时钟信号产生具有一个或多个中间相位的一个或多个中间本地时钟信号，其中每个中间本地时钟信号具有耦合到一个或多个中间动态逻辑门的大约50％的占空比。结束本地时钟信号，具有终止相位和大约50％的占空比，其也从全局时钟信号产生并且耦合到结束动态逻辑门。单个本地时钟信号的相位与较早的相位本地时钟信号重叠大约等于下一个本地时钟信号的相位重叠的量。第一动态逻辑门，中间动态逻辑门和最后的动态逻辑门耦合，使得具有单个本地时钟信号和相位的单个动态逻辑门只能向下一个单独的动态逻辑门提供信号，使用下一个相位本地时钟信号，其中门可以串联耦合在一起，在反馈回路中或前馈回路中。

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