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    • 23. 发明授权
    • Integrated micromechanical sensor device
    • 集成微机械传感器装置
    • US5744719A
    • 1998-04-28
    • US619735
    • 1996-06-12
    • Wolfgang Werner
    • Wolfgang Werner
    • G01P15/125B81B3/00B81C1/00G01L9/00G01L9/04G01P15/08H01L29/84G01P15/00
    • B81B3/0013B81C1/00928G01P15/0802B81C2201/117G01P2015/0814
    • The integrated micromechanical sensor device contains a body with a substrate (1) on which an insulating layer (2) and thereon a monocrystalline silicon layer (3), are arranged, in which the silicon layer has trenches as far as the surface of the insulating layer, and the side walls of the trenches as well as the side of the silicon layer adjacent to the insulating layer have a first doping type (n.sup.+) and the silicon layer has a second doping type (n.sup.-) at least in a partial region of its remaining surface, in which the silicon layer has a transistor arrangement in a first region (TB) and a sensor arrangement in a second region (SB), for which the insulating layer (2) is partly removed under the second region. Such a sensor device has considerable advantages over known devices with regard to its properties and its production process.
    • PCT No.PCT / DE94 / 01092 Sec。 371日期:1996年6月12日 102(e)日期1996年6月12日PCT 1994年9月20日PCT公布。 公开号WO95 / 08775 1995年3月30日该集成微机械传感器装置包括具有衬底(1)的主体,其上布置有绝缘层(2)和其上的单晶硅层(3),其中硅层具有沟槽直到 绝缘层的表面和沟槽的侧壁以及与绝缘层相邻的硅层的侧面具有第一掺杂型(n +),并且硅层具有第二掺杂类型(n-), 至少在其剩余表面的部分区域中,其中硅层在第一区域(TB)中具有晶体管布置,以及在第二区域(SB)中的传感器布置,绝缘层(2)在其下部分地被去除 第二个地区。 相对于已知装置,这种传感器装置具有相对于其性质及其制造方法的优点。
    • 25. 发明授权
    • Bipolar memory cell with cross-connected transistors and an external
capacitance
    • 具有交叉连接晶体管和外部电容的双极性存储单元
    • US4783765A
    • 1988-11-08
    • US898695
    • 1986-08-21
    • Wolfgang Werner
    • Wolfgang Werner
    • G11C11/41G11C11/411G11C7/00
    • G11C11/4116
    • An integrated bipolar memory cell with random access, includes an upper word line, a lower word line, two bit lines, two transistors each having two emitters, a base and a collector fed back crosswise to the base of the other transistor, two Schottky diodes, two low-resistance load resistors each forming a series circuit with a respective one of the Schottky diodes, two high-resistance load resistors each forming a parallel circuit with a respective one of the series circuits, each of the parallel circuits being connected between a respective one of the collectors and the upper word line defining active regions of the memory cell, one of the emitters of each of the transistors being connected to the lower word line, the other of the emitters of each of the transistors being connected to a respective one of the bit lines, and an external capacitance connected between the collectors outside the active regions.
    • 具有随机存取的集成双极性存储单元包括一个上部字线,一个下部字线,两个位线,两个具有两个发射极的晶体管,一个基极和一个集电极与另一个晶体管的基极交叉反馈,两个肖特基二极管 两个低电阻负载电阻器,每个与各自的肖特基二极管形成串联电路,两个高电阻负载电阻器各自与各个串联电路形成并联电路,每个并联电路连接在一个 收集器中的相应一个和限定存储器单元的有源区域的上部字线,每个晶体管的发射极之一连接到下部字线,每个晶体管的另一个发射极连接到相应的 一个位线,以及连接在有源区域之外的集电极之间的外部电容。