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21. 发明授权

US06939793B1 Dual damascene integration scheme for preventing copper contamination of dielectric layer 有权
标题翻译：用于防止介电层铜污染的双镶嵌一体化方案
公开(公告)号：US06939793B1
公开(公告)日：2005-09-06
申请号：US10422784
申请日：2003-04-25
申请人： Lu You , Fei Wang , Christy Woo
发明人： Lu You , Fei Wang , Christy Woo
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76804 , H01L21/76813 , H01L21/76832 , H01L21/76834 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化层，第一扩散阻挡层，第二蚀刻停止层，第一介电层，第一蚀刻停止层，第二介电层，延伸穿过第二介电层的沟槽和第一蚀刻停止层层，以及延伸穿过第一介电层，第二蚀刻停止层和第一扩散阻挡层的通孔。第一扩散阻挡层设置在第一金属化层上。第二蚀刻停止层设置在第一扩散阻挡层之上并与第一扩散阻挡层隔开，并且第一介电层设置在第二蚀刻停止层上。通孔也可以有圆角。第三蚀刻停止层也可以设置在第一扩散阻挡层和第二蚀刻停止层之间。侧壁扩散阻挡层可以设置在通孔和沟槽的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。还公开了制造半导体器件的方法。

22. 发明授权

US06875664B1 Formation of amorphous carbon ARC stack having graded transition between amorphous carbon and ARC material 失效
标题翻译：在无定形碳和ARC材料之间具有渐变过渡的无定形碳ARC叠层的形成
公开(公告)号：US06875664B1
公开(公告)日：2005-04-05
申请号：US10230794
申请日：2002-08-29
申请人： Richard J. Huang , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Cyrus E. Tabery , Lu You
发明人： Richard J. Huang , Srikanteswara Dakshina-Murthy , Philip A. Fisher , Cyrus E. Tabery , Lu You
IPC分类号： H01L21/027 , H01L21/033 , H01L21/28 , H01L21/312 , H01L21/314 , H01L21/3213 , H01L21/336
CPC分类号： H01L21/3145 , H01L21/02115 , H01L21/02274 , H01L21/0276 , H01L21/0332 , H01L21/28123 , H01L21/312 , H01L21/3144 , H01L21/3146 , H01L21/32139
摘要： A method of forming an integrated circuit using an amorphous carbon hard mask involves providing an amorphous carbon material layer above a layer of conductive material and providing an anti-reflective coating (ARC) material layer above the amorphous carbon material. A transition region is formed intermediate the amorphous carbon material layer and the ARC material layer. The transition region has a concentration profile that provides a transition between the amorphous carbon material layer and the ARC material layer. A portion of the amorphous carbon material layer, the ARC material layer, and the transition region is removed to form a hard mask, and a feature is formed in the layer of conductive material according to the hard mask.
摘要翻译：使用无定形碳硬掩模形成集成电路的方法包括在导电材料层之上提供无定形碳材料层，并在无定形碳材料上方提供抗反射涂层（ARC）材料层。在无定形碳材料层和ARC材料层之间形成过渡区域。过渡区域具有提供无定形碳材料层和ARC材料层之间的转变的浓度分布。去除非晶碳材料层，ARC材料层和过渡区域的一部分以形成硬掩模，并且根据硬掩模在导电材料层中形成特征。

23. 发明申请

US20050048771A1 Hardmask employing multiple layers of silicon oxynitride 有权
标题翻译：使用多层氮氧化硅的硬掩模
公开(公告)号：US20050048771A1
公开(公告)日：2005-03-03
申请号：US10962907
申请日：2004-10-12
申请人： Pei-Yuan Gao , Lu You , Richard Huang
发明人： Pei-Yuan Gao , Lu You , Richard Huang
IPC分类号： H01L21/033 , H01L21/3213 , H01L21/44 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/0332 , H01L21/32139 , H01L2924/0002 , H01L2924/00
摘要： A bi-layer BARC/hardmask structure includes a layer of amorphous carbon and two or more distinct and independently formed layers of a PECVD material such as SiON formed on the amorphous carbon layer. By independently forming several layers of PECVD material, at least some pinholes that are present in the lowermost PECVD layer are closed by upper PECVD layers and therefore do not extend through all of the PECVD layers. As a result the upper surface of the uppermost PECVD layer has a lower pinhole density than the lower PECVD layer. This reduces photoresist poisoning by dopant in the amorphous carbon layer, and etching of the amorphous carbon layer by photoresist stripping chemistry.
摘要翻译：双层BARC /硬掩模结构包括非晶碳层和形成在无定形碳层上的诸如SiON的PECVD材料的两个或更多个不同且独立形成的层。通过独立地形成多层PECVD材料，存在于最低PECVD层中的至少一些针孔由上PECVD层封闭，因此不延伸穿过所有PECVD层。结果，最上面的PECVD层的上表面具有比下PECVD层更低的针孔密度。这减少了无定形碳层中的掺杂剂的光致抗蚀剂中毒，以及通过光刻胶剥离化学法蚀刻无定形碳层。

24. 发明授权

US06756672B1 Use of sic for preventing copper contamination of low-k dielectric layers 有权
标题翻译：使用sic来防止低k电介质层的铜污染
公开(公告)号：US06756672B1
公开(公告)日：2004-06-29
申请号：US09776750
申请日：2001-02-06
申请人： Lu You , Dawn M. Hopper , Suzette K. Pangrle
发明人： Lu You , Dawn M. Hopper , Suzette K. Pangrle
IPC分类号： H01L2348
CPC分类号： H01L21/76831 , H01L21/76802 , H01L21/76804 , H01L21/76813 , H01L23/5222 , H01L23/5226 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and a via extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The via can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from silicon carbide. A method of manufacturing the semiconductor device is also disclosed.
摘要翻译：半导体器件包括第一金属化水平，第一扩散阻挡层，第一蚀刻停止层，介电层和延伸穿过介电层的通孔，第一蚀刻停止层和第一扩散阻挡层。第一扩散阻挡层设置在第一金属化层上。第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。通孔也可以有圆角。侧壁扩散阻挡层可以设置在通孔的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。第一蚀刻停止层可以由碳化硅形成。还公开了制造半导体器件的方法。

25. 发明授权

US06756300B1 Method for forming dual damascene interconnect structure 有权
标题翻译：双镶嵌互连结构的形成方法
公开(公告)号：US06756300B1
公开(公告)日：2004-06-29
申请号：US10324259
申请日：2002-12-18
申请人： Fei Wang , Jerry Cheng , Lynne A. Okada , Minh Quoc Tran , Lu You
发明人： Fei Wang , Jerry Cheng , Lynne A. Okada , Minh Quoc Tran , Lu You
IPC分类号： H01L214763
CPC分类号： H01L21/76811 , H01L21/76813
摘要： For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material disposed over the via and trench mask materials. The via and trench mask materials exposed through the via opening of the via mask patterning material are etched away, and the via mask patterning material is etched away. A portion of the dielectric material exposed through the via opening is etched down to the underlying interconnect structure, and a portion of the dielectric material exposed through the trench opening is etched, to form the dual damascene opening.
摘要翻译：为了在介电材料内形成双镶嵌开口，在电介质材料上形成通孔掩模材料和沟槽掩模材料。通过沟槽掩模材料形成沟槽开口，并且通过布置在通孔和沟槽掩模材料上方的通孔掩模图案形成材料形成通孔开口。通过通孔掩模图形材料的通路孔露出的通孔和沟槽掩模材料被蚀刻掉，并且通孔掩模图案材料被蚀刻掉。通过通孔开口暴露的介电材料的一部分被蚀刻到下面的互连结构上，并且蚀刻通过沟槽开口露出的电介质材料的一部分，以形成双镶嵌开口。

26. 发明授权

US06750127B1 Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance 有权
标题翻译：使用具有改善的耐蚀性的非晶碳制造半导体器件的方法
公开(公告)号：US06750127B1
公开(公告)日：2004-06-15
申请号：US10367407
申请日：2003-02-14
申请人： Mark S. Chang , Darin Chan , Chih Yuh Yang , Lu You , Scott A. Bell , Srikanteswara Dakshina-Murthy , Douglas J. Bonser
发明人： Mark S. Chang , Darin Chan , Chih Yuh Yang , Lu You , Scott A. Bell , Srikanteswara Dakshina-Murthy , Douglas J. Bonser
IPC分类号： H01L213205
CPC分类号： H01L21/32139 , H01L21/0332 , H01L21/0337
摘要： An amorphous carbon layer is implanted with one or more dopants that enhance the etch resistivity of the amorphous carbon to etchants such as chlorine and HBr that are typically used to etch polysilicon. Such a layer may be pattern to form a handmask for etching polysilicon that provides improved pattern transfer accuracy compared to conventional undoped amorphous carbon.
摘要翻译：注入一个或多个掺杂剂的无定形碳层，其增强无定形碳对通常用于蚀刻多晶硅的蚀刻剂如氯和HBr的蚀刻电阻率。这样的层可以被图案化以形成用于蚀刻多晶硅的手掩模，其与常规未掺杂的无定形碳相比提供改进的图案转印精度。

27. 发明授权

US06632707B1 Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning 有权
标题翻译：使用CVD有机BARC形成互连结构以减轻中毒的方法
公开(公告)号：US06632707B1
公开(公告)日：2003-10-14
申请号：US10058227
申请日：2002-01-29
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , James K. Kai , Calvin T. Gabriel , Lu You
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , James K. Kai , Calvin T. Gabriel , Lu You
IPC分类号： H01L2144
CPC分类号： H01L21/76808
摘要： A method for forming a metal interconnect structure in a semiconductor device with the elimination of via poisoning during trench mask formation employs a CVD organic BARC that isolates the low k dielectric film. The CVD organic BARC is deposited over the low k dielectric film and in the via hole. Once the trench mask has been formed on the CVD organic BARC, the CVD organic BARC may be removed in the same process as the photoresist of the trench mask layer. A properly formed trench will have been created since the via poisoning and resist scumming were substantially eliminated by the presence of the CVD organic BARC.
摘要翻译：在沟槽掩模形成期间消除通孔中毒的在半导体器件中形成金属互连结构的方法使用隔离低k绝缘膜的CVD有机BARC。 CVD有机BARC沉积在低k电介质膜和通孔中。一旦在CVD有机BARC上形成了沟槽掩模，就可以以与沟槽掩模层的光致抗蚀剂相同的工艺去除CVD有机BARC。由于CVD有机BARC的存在基本上消除了通孔中毒和抵抗浮渣，所以将形成一个正确形成的沟槽。

28. 发明授权

US06627973B1 Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory semiconductor device 有权
标题翻译：用于0.18微米闪存半导体器件的无空隙层间电介质（ILD0）
公开(公告)号：US06627973B1
公开(公告)日：2003-09-30
申请号：US10244129
申请日：2002-09-13
申请人： Minh Van Ngo , Robert A. Huertas , Lu You , King Wai Kelwin Ko , Pei-Yuan Gao
发明人： Minh Van Ngo , Robert A. Huertas , Lu You , King Wai Kelwin Ko , Pei-Yuan Gao
IPC分类号： H01L29167
CPC分类号： H01L21/02271 , C23C16/401 , H01L21/02129 , H01L21/022 , H01L21/31625 , H01L21/76801
摘要： A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology. A low dopant/TEOS flow performed at a higher pressure during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. Further, the present invention has the advantage of in-situ deposition of the void-free ILD0 layer of the 0.18-&mgr;m flash memory semiconductor device having a sound dopant concentration.
摘要翻译：一种消除0.18微米闪速存储器半导体器件的层间电介质材料中的空隙的方法和通过该方法形成的半导体器件。本发明提供一种通过使用非常低的沉积速率并且具有在约3k范围内的厚度的第一BPTEOS层来消除0.18微米快闪存储器半导体器件的层间电介质中的空隙的方法; 并提供第二BPTEOS层，使用标准沉积速率并且具有在约13k范围内的厚度，其中两层的原子掺杂剂浓度为约4.5％B和约5％P。这两步沉积过程完全消除了0.5-mum距离（栅极到栅极）的ILD中的空隙以及将来闪存技术的0.38μm距离（栅极到栅极）。在第一层沉积期间在较高压力下执行的低掺杂剂/ TEOS流提供了优异的间隙填充能力，其消除了排尿。此外，本发明的优点是具有声掺杂剂浓度的0.18μm的闪存半导体器件的无空隙的ILD0层的原位沉积。

29. 发明授权

US06489253B1 Method of forming a void-free interlayer dielectric (ILD0) for 0.18-&mgr;m flash memory technology and semiconductor device thereby formed 失效
标题翻译：由此形成用于0.18微米快闪存储器技术的无空隙层间电介质（ILD0）和由此形成的半导体器件的方法
公开(公告)号：US06489253B1
公开(公告)日：2002-12-03
申请号：US09788045
申请日：2001-02-16
申请人： Minh Van Ngo , Robert A. Huertas , Lu You , King Wai Kelwin Ko , Pei-Yuan Gao
发明人： Minh Van Ngo , Robert A. Huertas , Lu You , King Wai Kelwin Ko , Pei-Yuan Gao
IPC分类号： H01L21469
CPC分类号： H01L21/02271 , C23C16/401 , H01L21/02129 , H01L21/022 , H01L21/31625 , H01L21/76801
摘要： A method of eliminating voids in the interlayer dielectric material of 0.18-&mgr;m flash memory semiconductor devices and a semiconductor device formed by the method. The present invention provides a method for eliminating voids in the interlayer dielectric of a 0.18-&mgr;m flash memory semiconductor device by providing a first BPTEOS layer, using a very low deposition rate and having a thickness in a range of approximately 3 kÅ; and providing a second BPTEOS layer, using a standard deposition rate and having a thickness in a range of approximately 13 kÅ, wherein both layers have an atomic dopant concentration of approximately 4.5% B and approximately 5% P. This two-step deposition process completely eliminates voids in the ILD for a 0.5-&mgr;m distance (gate-to-gate) as well as 0.38-&mgr;m distance (gate-to-gate) which is the future flash technology. A low dopant/TEOS flow performed at a higher pressure during the deposition of the first layer provides an excellent gap-filling capability which eliminates voiding. Further, the present invention has the advantage of in-situ deposition of the void-free ILD0 layer of the 0.18-&mgr;m flash memory semiconductor device having a sound dopant concentration.
摘要翻译：一种消除0.18微米闪速存储器半导体器件的层间电介质材料中的空隙的方法和通过该方法形成的半导体器件。本发明提供一种通过使用非常低的沉积速率并且具有在约3k范围内的厚度的第一BPTEOS层来消除0.18微米快闪存储器半导体器件的层间电介质中的空隙的方法; 并提供第二BPTEOS层，使用标准沉积速率并且具有在约13k范围内的厚度，其中两层的原子掺杂剂浓度为约4.5％B和约5％P。这两步沉积过程完全消除了0.5-mum距离（栅极到栅极）的ILD中的空隙以及将来闪存技术的0.38μm距离（栅极到栅极）。在第一层沉积期间在较高压力下执行的低掺杂剂/ TEOS流提供了优异的间隙填充能力，其消除了排尿。此外，本发明的优点是具有声掺杂剂浓度的0.18μm的闪存半导体器件的无空隙的ILD0层的原位沉积。

30. 发明授权

US06335533B1 Electron microscopy sample having silicon nitride passivation layer 失效
标题翻译：具有氮化硅钝化层的电子显微镜样品
公开(公告)号：US06335533B1
公开(公告)日：2002-01-01
申请号：US09206674
申请日：1998-12-07
申请人： Guarionex Morales , Dawn Hopper , Lu You
发明人： Guarionex Morales , Dawn Hopper , Lu You
IPC分类号： H01J3700
CPC分类号： G01N1/32 , H01J2237/28
摘要： A transmission electron microscopy (TEM) or scanning electron microscopy (SEM) sample preparation method includes the steps of depositing a metal layer on top of a substrate, depositing a silicon nitride passivation layer on top of the metal layer, and cutting the substrate and the metal and passivation layers to expose their cross-sections for examination by electron microscopy. As a result, a TEM/SEM sample having sharp, well-defined boundaries is produced.
摘要翻译：透射电子显微镜（TEM）或扫描电子显微镜（SEM）样品制备方法包括以下步骤：在衬底的顶部上沉积金属层，在金属层的顶部上沉积氮化硅钝化层，以及切割衬底和金属和钝化层以暴露其横截面以通过电子显微镜检查。结果，产生具有清晰明确界限的TEM / SEM样品。

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