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21. 发明授权

US06265771B1 Dual chip with heat sink 有权
标题翻译：双芯片带散热片
公开(公告)号：US06265771B1
公开(公告)日：2001-07-24
申请号：US09238492
申请日：1999-01-27
申请人： Thomas G. Ference , Wayne J. Howell , Edmund J. Sprogis
发明人： Thomas G. Ference , Wayne J. Howell , Edmund J. Sprogis
IPC分类号： H01L2310
CPC分类号： H01L23/4334 , H01L23/3677 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L2224/05599 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48145 , H01L2224/48227 , H01L2224/48247 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2225/06568 , H01L2225/06582 , H01L2225/06586 , H01L2225/06589 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/181 , H01L2924/18301 , H01L2924/19041 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： An apparatus for simultaneously removing heat from two surfaces of a semiconductor structure includes a heat sink mounted to a front surface and a heat sink mounted to a back surface of the semiconductor structure. The structure can be two chips mounted in face-to-face arrangement, and the heat sinks remove heat from back surfaces of both chips.
摘要翻译：同时从半导体结构的两个表面去除热量的装置包括安装到前表面的散热器和安装到半导体结构的后表面的散热片。该结构可以是以面对面布置安装的两个芯片，并且散热器从两个芯片的背面去除热量。

22. 发明授权

US06545330B1 On chip alpha-particle detector 有权
公开(公告)号：US06545330B1
公开(公告)日：2003-04-08
申请号：US09614234
申请日：2000-07-12
申请人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
发明人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
IPC分类号： H01L2714
CPC分类号： H01L27/14683 , G01T1/244 , H01L27/14659 , H01L31/115 , H01L31/118
摘要： An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said particle emissions. In one embodiment of the present invention, the source comprises a solder ball that is formed on a surface of the IC chip, and the solder ball is capable of emitting alpha-particles. The particle emissions detector of the present invention is a reverse biased Schottky diode. The IC chip is formed by (a) providing an IC chip having at least one layer of particle sensitive circuitry formed therein; (b) forming another layer having at least one particle sensor region situated therein on a surface of said IC chip; and (c) optionally, forming at least one particle emission source over said another layer.

23. 发明授权

US06288559B1 Semiconductor testing using electrically conductive adhesives 失效
标题翻译：使用导电胶的半导体测试
公开(公告)号：US06288559B1
公开(公告)日：2001-09-11
申请号：US09050820
申请日：1998-03-30
申请人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
发明人： William E. Bernier , Michael A. Gaynes , Wayne J. Howell , Mark V. Pierson , Ajit K. Trivedi , Charles G. Woychik
IPC分类号： G01R3102
CPC分类号： G01R31/2886 , H01L2224/45144 , H01L2224/81385 , H01L2224/83101 , H05K3/321 , H01L2924/00
摘要： A method and device for testing and burning-in semiconductor circuits. The method and device permit the entire wafer to be tested by temporarily attaching the wafer to a test substrate using electrically conductive adhesive (ECA). The ECA conforms to deviations from co-planarity of the contact points of both the wafer and test substrate while providing a quality electrical connection at each point. ECA material can be deposited on either the wafer contacts or the substrate pads. In addition, the ECA may be deposited on C4 bumps or tin-capped lead bases. Variations in the method and device include filling vias of a non-conductive interposer with ECA. The electrical connection may be enhanced by forming conductive dendrites on test pads while the ECA is deposited on the wafer contacts. To further enhance the electrical connection, the ECA material can be plasma etched to remove some of its polymer matrix and to expose the electrically conductive particles on one side and then plating with palladium. After the palladium-plated ECA is brought into contact with aluminum pads, palladium-coated aluminum pads, or even C4 solder bumps, conductive dendrites are formed on the palladium-treated ECA bumps.
摘要翻译：一种用于测试和燃烧半导体电路的方法和装置。该方法和装置允许通过使用导电粘合剂（ECA）将晶片临时附接到测试基板来测试整个晶片。 ECA符合晶片和测试基板的接触点的共平面偏差，同时在每个点提供质量电连接。 ECA材料可以沉积在晶片触点或衬底焊盘上。此外，ECA可以沉积在C4凸点或锡盖铅基上。该方法和装置的变化包括用ECA填充非导电插入件的通孔。可以通过在测试焊盘上形成导电枝晶而增加电连接，同时将ECA沉积在晶片触点上。为了进一步增强电连接，可以对ECA材料进行等离子体蚀刻以除去其一些聚合物基质并使一面上的导电颗粒暴露，然后用钯镀覆。在镀钯的ECA与铝焊盘，钯涂覆的铝焊盘或甚至C4焊料凸块接触之后，在钯处理的ECA凸块上形成导电枝晶。

24. 发明授权

US06915795B2 Method and system for dicing wafers, and semiconductor structures incorporating the products thereof 失效
标题翻译：用于切割晶片的方法和系统，以及结合其产品的半导体结构
公开(公告)号：US06915795B2
公开(公告)日：2005-07-12
申请号：US10448305
申请日：2003-05-30
申请人： Donald W. Brouillette , Robert F. Cook , Thomas G. Ference , Wayne J. Howell , Eric G. Liniger , Ronald L. Mendelson
发明人： Donald W. Brouillette , Robert F. Cook , Thomas G. Ference , Wayne J. Howell , Eric G. Liniger , Ronald L. Mendelson
IPC分类号： B23D59/00 , B28D5/02 , H01L21/301 , H01L21/607 , H01L21/78 , H01L29/06 , B28D1/04
CPC分类号： H01L24/85 , B23D59/002 , B28D5/022 , H01L21/78 , H01L24/48 , H01L29/0657 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/78302 , H01L2224/85 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01018 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01077 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/10158 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , Y10T83/0259 , Y10T83/0378 , Y10T83/0581 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.
摘要翻译：一种用于切割半导体晶片的方法和系统，其提供具有大大减小的背面切屑和开裂的结构，以及增加的模具强度。还包括从根据本发明切割的晶片获得的半导体芯片结构。

25. 发明授权

US06611050B1 Chip edge interconnect apparatus and method 失效
标题翻译：芯片边缘互连设备和方法
公开(公告)号：US06611050B1
公开(公告)日：2003-08-26
申请号：US09538636
申请日：2000-03-30
申请人： Thomas G. Ference , Wayne J. Howell , William R. Tonti , Richard Q. Williams
发明人： Thomas G. Ference , Wayne J. Howell , William R. Tonti , Richard Q. Williams
IPC分类号： H01L2302
CPC分类号： H01L23/5388 , H01L21/561 , H01L21/78 , H01L23/3178 , H01L23/3185 , H01L24/03 , H01L24/11 , H01L25/0655 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0391 , H01L2224/0401 , H01L2224/05 , H01L2224/05567 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/11312 , H01L2224/11332 , H01L2224/11334 , H01L2224/1134 , H01L2224/13 , H01L2224/13021 , H01L2224/13023 , H01L2224/13027 , H01L2224/131 , H01L2224/1329 , H01L2224/133 , H01L2224/16 , H01L2224/16054 , H01L2224/16105 , H01L2224/16137 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/94 , H01L2924/0002 , H01L2924/01029 , H01L2924/14 , H01L2924/00014 , H01L2224/11 , H01L2224/03 , H01L2924/014 , H01L2224/05552 , H01L2924/00
摘要： The present invention provides a method of forming a low profile chip interconnection, and the interconnection so formed. A recessed contact area is formed at an edge of the wafer. A conductive material is deposited within the adjacent contact areas of each recess, thereby electrically connecting the two chips. The recess may have substantially perpendicular sides, or sloped sides.
摘要翻译：本发明提供一种形成低轮廓芯片互连的方法，以及形成的互连。在晶片的边缘处形成凹陷接触区域。导电材料沉积在每个凹槽的相邻接触区域内，从而电连接两个芯片。凹部可以具有大致垂直的侧面或倾斜的侧面。

26. 发明授权

US6104082A Metallization structure for altering connections 失效
标题翻译：改变连接的金属化结构
公开(公告)号：US6104082A
公开(公告)日：2000-08-15
申请号：US66147
申请日：1998-04-24
申请人： Claude L. Berlin , Wayne J. Howell
发明人： Claude L. Berlin , Wayne J. Howell
IPC分类号： H01L23/498 , H01L23/538 , H01L23/58
CPC分类号： H01L23/49827 , H01L23/5382 , H01L2224/05001 , H01L2224/05008 , H01L2224/051 , H01L2224/05548 , H01L2224/05569 , H01L2224/056 , H01L2224/16
摘要： A tailorable metallization level between a first set of pads connected to internal circuits of an electronic structure and a second set of pads for external connection provides for altering the configuration of the electronic structure. The second set of pads is kept invariant to facilitate external connection to the electronic structure. The reconfiguration scheme provides, in one embodiment, for sparing a stacked arrangement of chips. That is, it provides a way to disconnect a defective chip from a stack of chips and connect a spare chip so that, from the point of view of external circuitry, there is no change in the connection to or function of the stack. The invention also provides for changing the logical arrangement of circuits in a single chip, such as the organization of memory I/O.
摘要翻译：连接到电子结构的内部电路的第一组焊盘和用于外部连接的第二组焊盘之间的可裁剪的金属化级别提供了改变电子结构的配置。第二组焊盘保持不变，以便于外部连接到电子结构。在一个实施例中，重新配置方案提供了用于节省芯片的堆叠布置。也就是说，它提供了一种将有缺陷的芯片与一堆芯片断开连接的方法，并连接备用芯片，使得从外部电路的角度看，堆叠的连接或功能没有变化。本发明还提供了改变单个芯片中的电路的逻辑布置，诸如存储器I / O的组织。

27. 发明授权

US06806578B2 Copper pad structure 有权
标题翻译：铜垫结构
公开(公告)号：US06806578B2
公开(公告)日：2004-10-19
申请号：US09526394
申请日：2000-03-16
申请人： Wayne J. Howell , Ronald L. Mendelson , William T. Motsiff
发明人： Wayne J. Howell , Ronald L. Mendelson , William T. Motsiff
IPC分类号： H01L2348
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/0401 , H01L2224/05166 , H01L2224/05181 , H01L2224/05546 , H01L2224/05647 , H01L2224/13023 , H01L2224/13099 , H01L2224/13111 , H01L2924/0001 , H01L2924/01004 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01067 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/00014
摘要： A structure (and method) for a metallurgical structure includes a passivation layer, a via through the passivation layer extending to a metal line within the metallurgical structure, a barrier layer lining the via, a metal plug in the via above the barrier layer, the metal plug and the metal line comprising a same material, and a solder bump formed on the metal plug.
摘要翻译：用于冶金结构的结构（和方法）包括钝化层，通过钝化层延伸到金属结构内的金属线的通孔，衬套通孔的阻挡层，阻挡层上方的通孔中的金属塞，金属插塞和包含相同材料的金属线以及形成在金属插头上的焊料凸块。

28. 发明授权

US06645789B2 On chip alpha-particle detector 失效
公开(公告)号：US06645789B2
公开(公告)日：2003-11-11
申请号：US10246136
申请日：2002-09-18
申请人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
发明人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
IPC分类号： H01L2100
CPC分类号： H01L27/14683 , G01T1/244 , H01L27/14659 , H01L31/115 , H01L31/118
摘要： An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said particle emissions. In one embodiment of the present invention, the source comprises a solder ball that is formed on a surface of the IC chip, and the solder ball is capable of emitting alpha-particles. The particle emissions detector of the present invention is a reverse biased Schottky diode. The IC chip is formed by (a) providing an IC chip having at least one layer of particle sensitive circuitry formed therein; (b) forming another layer having at least one particle sensor region situated therein on a surface of said IC chip; and (c) optionally, forming at least one particle emission source over said another layer.

29. 发明授权

US06600213B2 Semiconductor structure and package including a chip having chamfered edges 失效
标题翻译：包括具有倒角边缘的芯片的半导体结构和封装
公开(公告)号：US06600213B2
公开(公告)日：2003-07-29
申请号：US09855617
申请日：2001-05-15
申请人： Donald W. Brouillette , Robert F. Cook , Thomas G. Ference , Wayne J. Howell , Eric G. Liniger , Ronald L. Mendelson
发明人： Donald W. Brouillette , Robert F. Cook , Thomas G. Ference , Wayne J. Howell , Eric G. Liniger , Ronald L. Mendelson
IPC分类号： H01L2906
CPC分类号： H01L24/85 , B23D59/002 , B28D5/022 , H01L21/78 , H01L24/48 , H01L29/0657 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/78302 , H01L2224/85 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01018 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01077 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/10158 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , Y10T83/0259 , Y10T83/0378 , Y10T83/0581 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A semiconductor structure with greatly reduced backside chipping and cracking, as well as increased die strength, accommodation of compact assembly with a carrier such as another semiconductor chip, and resistance to package damage is provided by dicing chips from a wafer in a manner that chamfers edges of the chips. Similar advantages are obtained in multi-chip structure.
摘要翻译：通过以下方式提供具有大大降低的背面切屑和开裂的半导体结构以及增加的模具强度，具有诸如另一半导体芯片的载体的紧凑组件和对封装损坏的抵抗性的切割芯片，的芯片。在多芯片结构中也有类似的优点。

30. 发明授权

US06271102B1 Method and system for dicing wafers, and semiconductor structures incorporating the products thereof 失效
公开(公告)号：US06271102B1
公开(公告)日：2001-08-07
申请号：US09032151
申请日：1998-02-27
申请人： Donald W. Brouillette , Robert F. Cook , Thomas G. Ference , Wayne J. Howell , Eric G. Liniger , Ronald L. Mendelson
发明人： Donald W. Brouillette , Robert F. Cook , Thomas G. Ference , Wayne J. Howell , Eric G. Liniger , Ronald L. Mendelson
IPC分类号： H01L21301
CPC分类号： H01L24/85 , B23D59/002 , B28D5/022 , H01L21/78 , H01L24/48 , H01L29/0657 , H01L2224/16 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/78302 , H01L2224/85 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01018 , H01L2924/01023 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01077 , H01L2924/01082 , H01L2924/014 , H01L2924/10155 , H01L2924/10158 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , Y10T83/0259 , Y10T83/0378 , Y10T83/0581 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A method and system for dicing a semiconductor wafer providing a structure with greatly reduced backside chipping and cracking, as well as increased die strength. Semiconductor chip structures obtained from wafers diced according to this invention are also encompassed.

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