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21. 发明授权

US07529224B2 Scheduler, network processor, and methods for weighted best effort scheduling 失效
标题翻译：调度器，网络处理器和加权最佳努力调度的方法
公开(公告)号：US07529224B2
公开(公告)日：2009-05-05
申请号：US11108485
申请日：2005-04-18
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
IPC分类号： H04L12/28
CPC分类号： H04L47/568 , H04L45/00 , H04L45/60 , H04L47/50 , H04L47/527
摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a three-entry calendar structure provides for weighted best effort scheduling. Each of a plurality different flows has an associated schedule control block. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a weight according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its weight, the schedule control block is temporarily removed from further scheduling.
摘要翻译：公开了一种用于在网络处理器中调度数据分组的系统和方法。实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。在一个实施例中，三入口日历结构提供加权最佳努力调度。多个不同的流中的每一个具有相关的进度控制块。计划控制块作为链表存储在先进先出缓冲区中。通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。每个调度控制块具有计数器，并根据相应分组所属的流的带宽优先级分配权重。每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。当调度控制块的递增计数器等于其权重时，调度控制块暂时从进一步调度中移除。

22. 发明申请

US20080147995A1 SYSTEMS AND METHODS FOR MULTI-FRAME CONTROL BLOCKS 有权
标题翻译：多框控制块的系统和方法
公开(公告)号：US20080147995A1
公开(公告)日：2008-06-19
申请号：US12039304
申请日：2008-02-28
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
IPC分类号： G06F12/00
CPC分类号： H04L49/901 , H04L49/252 , H04L49/30 , H04L49/90 , H04L69/12 , H04L69/22
摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.
摘要翻译：公开了一种用于在网络处理器中实现多帧控制块的系统和方法。实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

23. 发明授权

US07603539B2 Systems and methods for multi-frame control blocks 有权
标题翻译：多帧控制块的系统和方法
公开(公告)号：US07603539B2
公开(公告)日：2009-10-13
申请号：US12039304
申请日：2008-02-28
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
IPC分类号： G06F12/00
CPC分类号： H04L49/901 , H04L49/252 , H04L49/30 , H04L49/90 , H04L69/12 , H04L69/22
摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.
摘要翻译：公开了一种用于在网络处理器中实现多帧控制块的系统和方法。实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

24. 发明授权

US07376809B2 Systems and methods for multi-frame control blocks 有权
标题翻译：多帧控制块的系统和方法
公开(公告)号：US07376809B2
公开(公告)日：2008-05-20
申请号：US11076218
申请日：2005-03-09
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
IPC分类号： G06F12/02
CPC分类号： H04L49/901 , H04L49/252 , H04L49/30 , H04L49/90 , H04L69/12 , H04L69/22
摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.
摘要翻译：公开了一种用于在网络处理器中实现多帧控制块的系统和方法。实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

25. 发明授权

US06898179B1 Network processor/software control architecture 失效
标题翻译：网络处理器/软件控制架构
公开(公告)号：US06898179B1
公开(公告)日：2005-05-24
申请号：US09544896
申请日：2000-04-07
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Mark Anthony Rinaldi , Michael Steven Siegel , Colin Beaton Verrilli , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Mark Anthony Rinaldi , Michael Steven Siegel , Colin Beaton Verrilli , Fabrice Jean Verplanken
IPC分类号： G06F11/00 , H04B7/216 , H04L1/16 , H04L12/26
CPC分类号： G06F15/17
摘要： The transport protocol for communicating between general purpose processors acting as contact points and network processors in a packet processing environment such as Ethernet is provided. In such an environment, there is at least one single control point processor (CP) and a plurality of network processors (NP), sometimes referred to as blades. A typical system could contain two to sixteen network processors, and each network processor connects to a plurality of devices which communicate with each other over a network transport, such as Ethernet. The CP typically controls the functionality and the functioning of the network processors to function in a way that connects one end user with another, whether or not the end user is on the same network processor or a different network processor. There are three types of communication provided; first, there is communication generally referred to as control services and normally there will be only one pico processor which operates as a GCH (guided cell handler) and only one that operates as a guided tree handler (GTH). A path is provided for the controls to the GCH and the GTH commands, and a separate path is provided for the data frames between the GDH's (general data handler) and the CP.
摘要翻译：提供了用于在诸如以太网的分组处理环境中用作接触点的通用处理器和网络处理器之间进行通信的传输协议。在这样的环境中，存在至少一个单个控制点处理器（CP）和多个网络处理器（NP），有时称为刀片。典型的系统可以包含两到十六个网络处理器，并且每个网络处理器连接到通过诸如以太网的网络传输彼此通信的多个设备。 CP通常控制网络处理器的功能和功能，以使终端用户与另一终端用户相连的方式起作用，无论终端用户是否在同一个网络处理器或不同的网络处理器上。提供三种通讯方式; 首先，通常被称为控制服务的通信，并且通常将只有一个微微处理器作为GCH（引导的单元处理器）操作，并且只有一个作为引导树处理器（GTH）操作。为GCH和GTH命令的控制提供路径，并为GDH（通用数据处理程序）和CP之间的数据帧提供单独的路径。

26. 发明授权

US07293158B2 Systems and methods for implementing counters in a network processor with cost effective memory 失效
标题翻译：在具有成本效益的存储器的网络处理器中实现计数器的系统和方法
公开(公告)号：US07293158B2
公开(公告)日：2007-11-06
申请号：US11070060
申请日：2005-03-02
申请人： Jean Louis Calvignac , Chih-jen Chang , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Jean Louis Calvignac , Chih-jen Chang , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： G06F15/00 , G06F12/00
CPC分类号： H04L49/901 , H04L49/90
摘要： Systems and methods for implementing counters in a network processor with cost effective memory are disclosed. Embodiments include systems and methods for implementing counters in a network processor using less expensive memory such as DRAM. A network processor receives packets and implements accounting functions including counting packets in each of a plurality of flow queues. Embodiments include a counter controller that may increment counter values more than once during a R-M-W cycle. Each time a counter controller receives a request to update a counter during a R-M-W cycle that has been initiated for the counter, the counter controller increments the counter value received from memory. The incremented value is written to memory during the write cycle of the R-M-W cycle. A write disable unit disables writes that would otherwise occur during R-M-W cycles initiated for the counter during the earlier initiated R-M-W cycle.
摘要翻译：公开了在具有成本效益的存储器的网络处理器中实现计数器的系统和方法。实施例包括用于在使用诸如DRAM的廉价存储器的网络处理器中实现计数器的系统和方法。网络处理器接收分组并实现计费功能，包括在多个流队列中的每一个中计数分组。实施例包括可以在R-M-W周期期间多次增加计数器值的计数器控制器。每当计数器控制器在已经为计数器启动的R-M-W周期期间接收到更新计数器的请求时，计数器控制器递增从存储器接收的计数器值。在R-M-W周期的写周期期间，递增的值被写入存储器。写禁止单元禁用在较早启动的R-M-W周期期间为计数器启动的R-M-W周期期间将发生的写入。

27. 发明授权

US07904617B2 Indicating data buffer by last bit flag 失效
标题翻译：用最后一位标志指示数据缓冲区
公开(公告)号：US07904617B2
公开(公告)日：2011-03-08
申请号：US12100739
申请日：2008-04-10
申请人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： G06F5/00 , G06F15/16
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3018 , H04L49/90 , H04L49/9094
摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one” or “zero” and indicates when the data buffer having the last bit is transmitted. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.
摘要翻译：提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。每个控制块具有最后一位特征，其是可设置为“一”或“零”的单个位，并且指示何时发送具有最后位的数据缓冲器。当附加数据缓冲器被链接到先前的数据缓冲器，指示要发送附加数据缓冲器时，最后一位处于第一位置，而当没有附加数据缓冲器被链接到先前数据缓冲器时，最后一位处于第一位置。最后一位的位置被传送到指示特定帧的结束的网络处理器。

28. 发明授权

US07627701B2 Indicating last data buffer by last bit flag bit 有权
标题翻译：用最后一位标志位指示最后一个数据缓冲区
公开(公告)号：US07627701B2
公开(公告)日：2009-12-01
申请号：US12120419
申请日：2008-05-14
申请人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： G06F5/00 , G06F15/16
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3018 , H04L49/90 , H04L49/9094
摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.
摘要翻译：提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器的特定框架。

29. 发明授权

US06836480B2 Data structures for efficient processing of multicast transmissions 有权
标题翻译：用于多播传输的高效处理的数据结构
公开(公告)号：US06836480B2
公开(公告)日：2004-12-28
申请号：US09839079
申请日：2001-04-20
申请人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： H04L1256
CPC分类号： H04L49/901 , H04L12/1881 , H04L47/10 , H04L47/20 , H04L49/90
摘要： Data structures, a method, and an associated transmission system for multicast transmission on network processors in order both to minimize multicast transmission memory requirements and to account for port performance discrepancies. Frame data for multicast transmission on a network processor is read into buffers to which are associated various control structures and a reference frame. The reference frame and the associated control structures permit multicast targets to be serviced without creating multiple copies of the frame. Furthermore this same reference frame and control structures allow buffers allocated for each multicast target to be returned to the free buffer queue without waiting until all multicast transmissions are complete.
摘要翻译：数据结构，方法和相关的传输系统，用于网络处理器上的组播传输，以便最大限度地减少组播传输内存的需求并解决端口性能差异。将网络处理器上的组播传输的帧数据读入与各种控制结构和参考帧相关联的缓冲器。参考帧和相关联的控制结构允许在不创建帧的多个拷贝的情况下对多播目标进行服务。此外，相同的参考帧和控制结构允许为每个多播目标分配的缓冲区返回到空闲缓冲器队列，而不等待所有多播传输完成。

30. 发明申请

US20080229272A1 DATA ALIGNER IN RECONFIGURABLE COMPUTING ENVIRONMENT 失效
公开(公告)号：US20080229272A1
公开(公告)日：2008-09-18
申请号：US12126953
申请日：2008-05-26
申请人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
发明人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
IPC分类号： G06F17/50 , G06F15/16
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.

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