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    • 25. 发明申请
    • SATA primitive prediction and correction
    • SATA原始预测和校正
    • US20070189619A1
    • 2007-08-16
    • US11456077
    • 2006-07-06
    • Chuan LiuPao-Ching Tseng
    • Chuan LiuPao-Ching Tseng
    • G06K9/36
    • G06F11/1004
    • A method of correcting corrupted primitives transmitted between a serial advanced technology attachment (SATA) host and a SATA device includes detecting the presence of a corrupted primitive; analyzing a current state, a previously transmitted primitive, or a previously received primitive; selecting at least one candidate primitive according to at least one of the current state, the previously transmitted primitive, and the previously received primitive; predicting the identity of the corrupted primitive according to at least one candidate primitive and the corrupted primitive; and replacing the corrupted primitive with the predicted primitive.
    • 一种校正在串行高级技术附件(SATA)主机和SATA设备之间传输的损坏的原语的方法包括检测损坏的原语的存在; 分析当前状态,先前传输的原语或先前接收的原语; 根据当前状态,先前传输的原语和先前接收到的原语中的至少一个,选择至少一个候选基元; 根据至少一个候选原语和损坏的原语预测损坏的原语的身份; 并用预测的原语替换被破坏的原语。
    • 29. 发明授权
    • Signal generating circuit capable of generating a validation signal and related method thereof
    • 能产生验证信号的信号发生电路及其相关方法
    • US07272673B2
    • 2007-09-18
    • US11163899
    • 2005-11-03
    • Chuan LiuChuan-Cheng HsiaoJeng-Horng Tsai
    • Chuan LiuChuan-Cheng HsiaoJeng-Horng Tsai
    • G06F3/00
    • G06F13/385
    • A signal generating system for generating a validation signal includes: a phase lock loop (PLL) for locking an output clock to a specific clock frequency; and a digital signal generation circuit. The digital signal generating circuit includes: a triggering circuit, electrically coupled to the PLL, for determining whether the output clock of the PLL is in a frequency range, and outputting a triggering signal if the output clock is in a frequency range; and a signal generating device, electrically coupled to the triggering circuit and the PLL, for generating the validation signal according to the output clock when receiving the triggering signal; wherein before the output clock is in the frequency range, the PLL continuously outputs the output clock.
    • 用于产生确认信号的信号发生系统包括:用于将输出时钟锁定到特定时钟频率的锁相环(PLL); 和数字信号发生电路。 数字信号发生电路包括:电耦合到PLL的用于确定PLL的输出时钟是否在频率范围内的触发电路,以及如果输出时钟在频率范围内则输出触发信号; 以及信号发生装置,电耦合到所述触发电路和所述PLL,用于当接收到所述触发信号时根据所述输出时钟产生所述有效信号; 其中在输出时钟处于频率范围之前,PLL连续输出输出时钟。