专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20070267673A1 Adjustable on-chip sub-capacitor design 有权
标题翻译：可调片上子电容设计
公开(公告)号：US20070267673A1
公开(公告)日：2007-11-22
申请号：US11436249
申请日：2006-05-18
申请人： Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L27/108 , H01L29/94 , H01L29/76 , H01L31/119
CPC分类号： H01L27/0805 , H01L23/5223 , H01L27/0688 , H01L27/0808 , H01L2924/0002 , H01L2924/00
摘要： One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.
摘要翻译：一个或多个片上VNCAP或MIMCAP电容器利用可变MOS电容来改善电容器的均匀电容值。这允许生产硅半导体芯片，其上安装有具有精确调节的电容值的电容器在其设计值的约1％至5％的范围内。该优化可以通过使用一对用于DC去耦的可变MOS电容器之间的背对背连接来实现。它涉及VOCAP和/或MIMCAP电容器的片上BEOL电容的并联，通过在FEOL中插入成对的背对背可变MOS电容器。

22. 发明授权

US08273648B2 Circuit structures and methods with BEOL layers configured to block electromagnetic edge interference 有权
公开(公告)号：US08273648B2
公开(公告)日：2012-09-25
申请号：US13369592
申请日：2012-02-09
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic
IPC分类号： H01L21/3205
CPC分类号： H01L23/5225 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in the first direction or the second direction to block electromagnetic interference of a particular wavelength from passing therethrough.

23. 发明授权

US07821110B2 Circuit structures and methods with BEOL layer(s) configured to block electromagnetic interference 有权
标题翻译： BEOL层的电路结构和方法被配置为阻止电磁干扰
公开(公告)号：US07821110B2
公开(公告)日：2010-10-26
申请号：US11747342
申请日：2007-05-11
申请人： Dae Ik Kim , Jonghae Kim , Moon Ju Kim , Choongyeun Cho
发明人： Dae Ik Kim , Jonghae Kim , Moon Ju Kim , Choongyeun Cho
IPC分类号： H01L23/552
CPC分类号： H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： Back end of line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic interference. One such BEOL circuit structure includes one or more semiconductor substrates supporting one or more integrated circuits, and one or more BEOL layers disposed over the semiconductor substrate(s). At least one BEOL layer includes a conductive pattern defined at least partially by a plurality of elements arrayed in a first direction and a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in at least one of the first and second directions to block electromagnetic interference of a particular wavelength from passing therethrough. In one implementation, a first conductive pattern of a first BEOL layer polarizes electromagnetic interference, and a second conductive pattern of a second BEOL layer blocks the polarized electromagnetic interference.
摘要翻译：提供后端（BEOL）电路结构和方法来阻止外部来源或内部产生的电磁干扰。一种这样的BEOL电路结构包括支撑一个或多个集成电路的一个或多个半导体衬底以及设置在半导体衬底之上的一个或多个BEOL层。至少一个BEOL层包括至少部分地由在第一方向和第二方向排列的多个元件至少部分地限定的导电图案。多个元件的大小和位置在第一和第二方向中的至少一个方向上，以阻止特定波长的电磁干扰通过。在一个实施方案中，第一BEOL层的第一导电图案使电磁干扰偏振，并且第二BEOL层的第二导电图案阻挡极化的电磁干扰。

24. 发明授权

US07791403B2 Transitioning digital integrated circuit from standby mode to active mode via backgate charge transfer 失效
标题翻译：通过背栅电荷转移将数字集成电路从待机模式转换到主动模式
公开(公告)号：US07791403B2
公开(公告)日：2010-09-07
申请号：US12206124
申请日：2008-09-08
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K19/0016 , Y10T29/49002
摘要： Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.
摘要翻译：提供了电路和方法，以便于将数字电路从背栅极偏置待机模式转换到主动模式。数字电路包括半导体衬底，至少部分地设置在半导体衬底中的一个或多个p型阱中的多个n沟道晶体管，至少部分地设置在半导体中的一个或多个n型阱中的多个p沟道晶体管基板和背栅控制电路。背栅控制电路电耦合到p型阱和n型阱，以便于将多个n沟道晶体管和多个p沟道晶体管从背栅极偏置待机模式转换到有源模式，通过自动将电荷从n型阱转移到p型阱，直到达到阱电压阈值，表明晶体管从背栅极偏置待机模式到活动模式的完成转变。

25. 发明授权

US07904494B2 Random number generator with random sampling 失效
标题翻译：随机数发生器随机抽样
公开(公告)号：US07904494B2
公开(公告)日：2011-03-08
申请号：US11608264
申请日：2006-12-08
申请人： Choongyeun Cho , Dae Ik Kim , Jonghae Kim , Moon J. Kim
发明人： Choongyeun Cho , Dae Ik Kim , Jonghae Kim , Moon J. Kim
IPC分类号： G06F1/02
CPC分类号： G06F7/588
摘要： In a random number generator, a first converter converts a first analog noise signal into a random digital clock signal and a second converter samples a second analog noise signal asynchronous to the first analog noise signal in response to the random digital clock signal and generates a random digital number stream. In one aspect, a random number generator output block samples the second converter random digital number stream in response to the random digital clock signal and generates a random number generator block output. In another aspect a pseudo noise source state machine generates the random digital clock signal in response to a first seed generated from the first analog noise signal, a second seed from process variation digital amplifier, and a past machine state.
摘要翻译：在随机数发生器中，第一转换器将第一模拟噪声信号转换为随机数字时钟信号，并且第二转换器响应于随机数字时钟信号对与第一模拟噪声信号异步的第二模拟噪声信号进行采样，并产生随机数数字数字流。一方面，随机数发生器输出块响应于随机数字时钟信号对第二转换器随机数字数字流进行采样，并产生随机数发生器块输出。在另一方面，伪噪声源状态机响应于从第一模拟噪声信号产生的第一种子，来自过程变化数字放大器的第二种子和过去的机器状态，产生随机数字时钟信号。

26. 发明授权

US07902880B2 Transitioning digital integrated circuit from standby mode to active mode via backgate charge transfer 有权
标题翻译：通过背栅电荷转移将数字集成电路从待机模式转换到主动模式
公开(公告)号：US07902880B2
公开(公告)日：2011-03-08
申请号：US12844339
申请日：2010-07-27
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim
IPC分类号： H01L25/00 , H03K19/00
CPC分类号： H03K19/0016 , Y10T29/49002
摘要： Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.
摘要翻译：提供了电路和方法，以便于将数字电路从背栅极偏置待机模式转换到主动模式。数字电路包括半导体衬底，至少部分地设置在半导体衬底中的一个或多个p型阱中的多个n沟道晶体管，至少部分地设置在半导体中的一个或多个n型阱中的多个p沟道晶体管基板和背栅控制电路。背栅控制电路电耦合到p型阱和n型阱，以便于将多个n沟道晶体管和多个p沟道晶体管从背栅极偏置待机模式转换到有源模式，通过自动将电荷从n型阱转移到p型阱，直到达到阱电压阈值，表明晶体管从背栅极偏置待机模式到活动模式的完成转变。

27. 发明授权

US08138563B2 Circuit structures and methods with BEOL layers configured to block electromagnetic edge interference 有权
标题翻译： BEOL层的电路结构和方法被配置为阻止电磁边缘干扰
公开(公告)号：US08138563B2
公开(公告)日：2012-03-20
申请号：US12188243
申请日：2008-08-08
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic
IPC分类号： H01L29/82
CPC分类号： H01L23/5225 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in the first direction or the second direction to block electromagnetic interference of a particular wavelength from passing therethrough.
摘要翻译：提供了后端行（BEOL）电路结构和方法来阻止外部来源或内部产生的电磁边缘干扰。一个这样的BEOL电路结构包括支撑一个或多个集成电路的半导体衬底和设置在半导体衬底上的多个BEOL层。多个BEOL层延伸到电路结构的边缘并且包括邻近电路结构的边缘布置的至少一个垂直延伸的导电图案。至少部分地由设置在多个BEOL层中的多个元件限定垂直延伸的导电图案。多个元件在电路结构的边缘沿其第一方向或第二方向均匀地排列在其至少一部分上。多个元件的大小和尺寸设置在第一方向或第二方向上，以阻止特定波长的电磁干扰通过。

28. 发明申请

US20080136697A1 METHOD AND SYSTEM FOR RANDOM NUMBER GENERATOR WITH RANDOM SAMPLING 失效
标题翻译：随机采样随机数发生器的方法与系统
公开(公告)号：US20080136697A1
公开(公告)日：2008-06-12
申请号：US11608264
申请日：2006-12-08
申请人： Choongyeun Cho , Dae Ik Kim , Jonghae Kim , Moon J. Kim
发明人： Choongyeun Cho , Dae Ik Kim , Jonghae Kim , Moon J. Kim
IPC分类号： G06F7/58
CPC分类号： G06F7/588
摘要： In a random number generator, a first converter converts a first analog noise signal into a random digital clock signal and a second converter samples a second analog noise signal asynchronous to the first analog noise signal in response to the random digital clock signal and generates a random digital number stream. In one aspect, a random number generator output block samples the second converter random digital number stream in response to the random digital clock signal and generates a random number generator block output. In another aspect a pseudo noise source state machine generates the random digital clock signal in response to a first seed generated from the first analog noise signal, a second seed from process variation digital amplifier, and a past machine state.
摘要翻译：在随机数发生器中，第一转换器将第一模拟噪声信号转换成随机数字时钟信号，并且第二转换器响应于随机数字时钟信号对与第一模拟噪声信号异步的第二模拟噪声信号进行采样，并产生随机数数字数字流。一方面，随机数发生器输出块响应于随机数字时钟信号对第二转换器随机数字数字流进行采样，并产生随机数发生器块输出。在另一方面，伪噪声源状态机响应于从第一模拟噪声信号产生的第一种子，来自过程变化数字放大器的第二种子和过去的机器状态，产生随机数字时钟信号。

29. 发明授权

US09013310B2 Circuit structure and method of fabrication for facilitating radio frequency identification (RFID) 有权
标题翻译：用于促进射频识别（RFID）的电路结构和制造方法
公开(公告)号：US09013310B2
公开(公告)日：2015-04-21
申请号：US12178894
申请日：2008-07-24
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim
IPC分类号： G08B13/14 , G06K19/077 , H01Q1/22 , H01Q1/24 , H01Q7/00 , H01Q23/00
CPC分类号： G06K19/07749 , H01Q1/2225 , H01Q1/248 , H01Q7/00 , H01Q23/00
摘要： A radio frequency identification (RFID) device and method of fabrication are presented. The RFID device includes an RFID antenna, a capacitor, and an RFID integrated circuit. The RFID antenna includes an elongate conductive trace disposed within an antenna area of the RFID device, and the capacitor includes an elongate capacitive structure for storing power. The elongate capacitive structure is aligned with the elongate conductive trace and embedded within the antenna area of the RFID device. The RFID integrated circuit is electrically coupled to the RFID antenna and to the capacitor, and the capacitor stores power within the antenna area of the RFID device to facilitate RFID integrated circuit functionality.
摘要翻译：提出了射频识别（RFID）装置及其制造方法。 RFID设备包括RFID天线，电容器和RFID集成电路。 RFID天线包括设置在RFID设备的天线区域内的细长导电迹线，并且电容器包括用于存储电力的细长电容结构。细长的电容结构与细长导电迹线对准，并且嵌入在RFID器件的天线区域内。 RFID集成电路电耦合到RFID天线和电容器，并且电容器在RFID设备的天线区域内存储功率以便于RFID集成电路功能。

30. 发明授权

US08723646B2 Acoustic wave and radio frequency identification device and method 失效
标题翻译：声波和射频识别装置及方法
公开(公告)号：US08723646B2
公开(公告)日：2014-05-13
申请号：US12210371
申请日：2008-09-15
申请人： Choongyeun Cho , Richard Ferri , Daeik Kim , Jonghae Kim , Moon Ju Kim
发明人： Choongyeun Cho , Richard Ferri , Daeik Kim , Jonghae Kim , Moon Ju Kim
IPC分类号： H04Q5/22
CPC分类号： H04Q9/00 , H04Q2209/47
摘要： An identification method and identification device are presented employing radio frequency and acoustic wave communication modes. The identification method includes: receiving at an acoustic wave and radio frequency identification device an acoustic wave signal of a first frequency and a radio frequency signal of a second frequency, where the acoustic wave signal and the radio frequency signal are received from an acoustic wave and radio frequency identification reader, and the first frequency and the second frequency are different frequencies; and responding to the receiving by transmitting at least one of an acoustic wave identification (AWID) or a radio frequency identification (RFID) from the acoustic wave and radio frequency identification device.
摘要翻译：采用射频和声波通信方式提出了识别方法和识别装置。识别方法包括：在声波和射频识别装置处接收第一频率的声波信号和从声波接收声波信号和射频信号的第二频率的射频信号，射频识别读取器，第一频率和第二频率是不同的频率; 以及通过从声波和射频识别装置发送声波识别（AWID）或射频识别（RFID）中的至少一个来响应于接收。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式