专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20130001707A1 FABRICATING METHOD OF MOS TRANSISTOR, FIN FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF 审中-公开
标题翻译： MOS晶体管的制造方法，Fin场效应晶体管及其制造方法
公开(公告)号：US20130001707A1
公开(公告)日：2013-01-03
申请号：US13174711
申请日：2011-06-30
申请人： Chien-Liang Lin , Ying-Wei Yen , Yu-Ren Wang , Chan-Lon Yang , Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
发明人： Chien-Liang Lin , Ying-Wei Yen , Yu-Ren Wang , Chan-Lon Yang , Chin-Cheng Chien , Chun-Yuan Wu , Chih-Chien Liu , Chin-Fu Lin , Teng-Chun Tsai
IPC分类号： H01L29/78 , H01L21/31
CPC分类号： H01L21/02332 , H01L29/512 , H01L29/66795 , H01L29/785
摘要： A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.
摘要翻译： MOS晶体管的制造方法包括以下步骤。提供基板。在基板上形成栅介电层。进行包含氮等离子体和氦气的氮化处理，以对栅介质层进行氮化。还提供了鳍状场效应晶体管及其制造方法。

22. 发明授权

US08324118B2 Manufacturing method of metal gate structure 有权
标题翻译：金属门结构的制造方法
公开(公告)号：US08324118B2
公开(公告)日：2012-12-04
申请号：US13072795
申请日：2011-03-28
申请人： Chih-Chien Liu , Chun-Yuan Wu , Chin-Fu Lin , Teng-Chun Tsai , Chin-Cheng Chien
发明人： Chih-Chien Liu , Chun-Yuan Wu , Chin-Fu Lin , Teng-Chun Tsai , Chin-Cheng Chien
IPC分类号： H01L21/31
CPC分类号： H01L29/517 , H01L21/28185 , H01L29/513 , H01L29/66545
摘要： A manufacturing method of a metal gate structure includes providing a substrate having at least a first metal oxide layer formed thereon, and transferring the surface of the first metal oxide layer into a second metal oxide layer. The first metal oxide layer includes a metal oxide (M1Ox) of a first metal (M1) and the second metal oxide layer includes a metal oxide ((M1M2Oy) of the first metal and a second metal (M2).
摘要翻译：金属栅极结构的制造方法包括提供具有形成在其上的至少第一金属氧化物层的基板，并将第一金属氧化物层的表面转移到第二金属氧化物层中。第一金属氧化物层包括第一金属（M1）的金属氧化物（M1Ox），第二金属氧化物层包括第一金属的金属氧化物（（M1M2Oy））和第二金属（M2）。

23. 发明申请

US20120244669A1 Method of Manufacturing Semiconductor Device Having Metal Gates 有权
标题翻译：制造具有金属门的半导体器件的方法
公开(公告)号：US20120244669A1
公开(公告)日：2012-09-27
申请号：US13053223
申请日：2011-03-22
申请人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yi-Wei Chen , Hsin-Fu Huang , Tzung-Ying Lee , Min-Chuan Tsai , Chan-Lon Yang , Chun-Yuan Wu , Teng-Chun Tsai , Guang-Yaw Hwang , Chia-Lin Hsu , Jie-Ning Yang , Cheng-Guo Chen , Jung-Tsung Tseng , Zhi-Cheng Lee , Hung-Ling Shih , Po-Cheng Huang , Yi-Wen Chen , Che-Hua Hsu
发明人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yi-Wei Chen , Hsin-Fu Huang , Tzung-Ying Lee , Min-Chuan Tsai , Chan-Lon Yang , Chun-Yuan Wu , Teng-Chun Tsai , Guang-Yaw Hwang , Chia-Lin Hsu , Jie-Ning Yang , Cheng-Guo Chen , Jung-Tsung Tseng , Zhi-Cheng Lee , Hung-Ling Shih , Po-Cheng Huang , Yi-Wen Chen , Che-Hua Hsu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823807 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.
摘要翻译：本发明提供一种制造具有金属栅极的半导体器件的方法。首先，提供基板。具有第一牺牲栅极的第一导电型晶体管和具有第二牺牲栅极的第二导电型晶体管设置在衬底上。去除第一牺牲栅极以形成第一沟槽。然后，在第一沟槽中形成第一金属层。去除第二牺牲栅极以形成第二沟槽。接下来，在第一沟槽和第二沟槽中形成第二金属层。最后，在第二金属层上形成第三金属层，其中第三金属层被填充到第一沟槽和第二沟槽中。

24. 发明授权

US08802524B2 Method of manufacturing semiconductor device having metal gates 有权
标题翻译：制造具有金属栅极的半导体器件的方法
公开(公告)号：US08802524B2
公开(公告)日：2014-08-12
申请号：US13053223
申请日：2011-03-22
申请人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yi-Wei Chen , Hsin-Fu Huang , Tzung-Ying Lee , Min-Chuan Tsai , Chan-Lon Yang , Chun-Yuan Wu , Teng-Chun Tsai , Guang-Yaw Hwang , Chia-Lin Hsu , Jie-Ning Yang , Cheng-Guo Chen , Jung-Tsung Tseng , Zhi-Cheng Lee , Hung-Ling Shih , Po-Cheng Huang , Yi-Wen Chen , Che-Hua Hsu
发明人： Po-Jui Liao , Tsung-Lung Tsai , Chien-Ting Lin , Shao-Hua Hsu , Yi-Wei Chen , Hsin-Fu Huang , Tzung-Ying Lee , Min-Chuan Tsai , Chan-Lon Yang , Chun-Yuan Wu , Teng-Chun Tsai , Guang-Yaw Hwang , Chia-Lin Hsu , Jie-Ning Yang , Cheng-Guo Chen , Jung-Tsung Tseng , Zhi-Cheng Lee , Hung-Ling Shih , Po-Cheng Huang , Yi-Wen Chen , Che-Hua Hsu
IPC分类号： H01L21/8238 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823842 , H01L21/823807 , H01L29/66545 , H01L29/6656 , H01L29/7833
摘要： The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench.
摘要翻译：本发明提供一种制造具有金属栅极的半导体器件的方法。首先，提供基板。具有第一牺牲栅极的第一导电型晶体管和具有第二牺牲栅极的第二导电型晶体管设置在衬底上。去除第一牺牲栅极以形成第一沟槽。然后，在第一沟槽中形成第一金属层。去除第二牺牲栅极以形成第二沟槽。接下来，在第一沟槽和第二沟槽中形成第二金属层。最后，在第二金属层上形成第三金属层，其中第三金属层被填充到第一沟槽和第二沟槽中。

25. 发明授权

US09567493B2 CMP slurry solution for hardened fluid material 有权
标题翻译：用于硬化流体材料的CMP浆液
公开(公告)号：US09567493B2
公开(公告)日：2017-02-14
申请号：US14261644
申请日：2014-04-25
申请人： Kuo-Yin Lin , Wen-Kuei Liu , Teng-Chun Tsai , Shen-Nan Lee , Kuo-Cheng Lien , Chang-Sheng Lin , Yu-Wei Chou
发明人： Kuo-Yin Lin , Wen-Kuei Liu , Teng-Chun Tsai , Shen-Nan Lee , Kuo-Cheng Lien , Chang-Sheng Lin , Yu-Wei Chou
IPC分类号： B44C1/22 , C09G1/18
CPC分类号： C09G1/14 , C09G1/02 , C09G1/04 , C09G1/18 , H01L21/0273 , H01L21/31055 , H01L21/31058 , H01L21/31133
摘要： A method for performing a Chemical Mechanical Polishing (CMP) process includes applying a CMP slurry solution to a surface of a hardened fluid material on a substrate, the solution comprising an additive to change a bonding structure on the surface of the hardened fluid material. The method further includes polishing the surface of the hardened fluid material with a polishing head.
摘要翻译：执行化学机械抛光（CMP）工艺的方法包括将CMP浆料溶液施加到基底上的硬化流体材料的表面上，该溶液包含改变硬化流体材料表面上的结合结构的添加剂。该方法还包括用研磨头抛光硬化的流体材料的表面。

26. 发明授权

US08536060B2 Method for clearing native oxide 有权
标题翻译：清除天然氧化物的方法
公开(公告)号：US08536060B2
公开(公告)日：2013-09-17
申请号：US13468042
申请日：2012-05-10
申请人： Yen-Chu Chen , Teng-Chun Tsai , Chien-Chung Huang , Keng-Jen Liu
发明人： Yen-Chu Chen , Teng-Chun Tsai , Chien-Chung Huang , Keng-Jen Liu
IPC分类号： H01L21/302 , C23F1/00
CPC分类号： H01L21/3065 , H01L21/02057 , H01L21/02063
摘要： A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.
摘要翻译：描述了清除天然氧化物的方法。提供了一种衬底，包括其中形成有自然氧化物层的暴露部分。使用三氟化氮（NF 3）和氨（NH 3）作为反应气体对基板进行清除处理，其中NF 3的体积流量大于NH 3的体积流量。

27. 发明申请

US20130011938A1 METHOD FOR MANUFACTURING THROUGH-SILICON VIA 有权
标题翻译：通过硅制造方法
公开(公告)号：US20130011938A1
公开(公告)日：2013-01-10
申请号：US13176790
申请日：2011-07-06
申请人： Wei-Che TSAO , Chia-Lin Hsu , Jen-Chieh Lin , Teng-Chun Tsai , Hsin-Kuo Hsu , Ya-Hsueh Hsieh , Ren-Peng Huang , Chih-Hsien Chen , Wen-Chin Lin , Yung-Lun Hsieh
发明人： Wei-Che TSAO , Chia-Lin Hsu , Jen-Chieh Lin , Teng-Chun Tsai , Hsin-Kuo Hsu , Ya-Hsueh Hsieh , Ren-Peng Huang , Chih-Hsien Chen , Wen-Chin Lin , Yung-Lun Hsieh
IPC分类号： H01L21/66 , H01L21/306 , H01L21/304
CPC分类号： H01L21/31053 , H01L21/3212 , H01L21/76898 , H01L22/12 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.
摘要翻译：一种制造TSV的方法，其中该方法包括以下几个步骤：提供具有基板和ILD层（层间电介质层）的堆叠结构，其中穿透ILD层并进一步延伸到基板中的开口是形成。在堆叠结构和开口的侧壁上形成绝缘体层和金属阻挡层之后，在堆叠结构上形成顶部金属层以实现开口。进行停止在阻挡层上的第一平面化处理以去除顶部金属层的一部分。随后进行停止在ILD层上的第二平坦化处理以去除金属阻挡层的一部分，绝缘体层的一部分和顶部金属层的一部分，其中第二平坦化工艺具有由光线确定的抛光终点干涉测量或电机电流。

28. 发明申请

US20120322265A1 POLY OPENING POLISH PROCESS 有权
公开(公告)号：US20120322265A1
公开(公告)日：2012-12-20
申请号：US13162776
申请日：2011-06-17
申请人： Chun-Wei HSU , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Chang-Hung Kung , Chia-His Chen , Yen-Ming Chen
发明人： Chun-Wei HSU , Po-Cheng Huang , Teng-Chun Tsai , Chia-Lin Hsu , Chih-Hsun Lin , Chang-Hung Kung , Chia-His Chen , Yen-Ming Chen
IPC分类号： H01L21/304 , H01L21/306
CPC分类号： H01L21/31053 , H01L21/02065 , H01L29/517 , H01L29/66545
摘要： A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.
摘要翻译：多孔抛光工艺包括以下步骤。提供半成品半导体元件。半成品半导体部件包括基板，设置在基板上的栅极和设置在基板上并覆盖栅极的电介质层。将第一抛光工艺施加到电介质层上。第二次抛光工艺应用于浇口。第二抛光工艺利用包含水溶性聚合物表面活性剂，碱性化合物和水的润湿溶液。多孔抛光工艺可有效去除化学机械抛光中形成的氧化物残留物，从而提高集成电路的性能，降低集成电路的生产成本。

29. 发明申请

US20120264302A1 CHEMICAL MECHANICAL POLISHING PROCESS 审中-公开
标题翻译：化学机械抛光工艺
公开(公告)号：US20120264302A1
公开(公告)日：2012-10-18
申请号：US13085502
申请日：2011-04-13
申请人： Chun-Wei Hsu , Teng-Chun Tsai , Chia-Lin Hsu , Po-Cheng Huang , Chia-Hsi Chen , Yen-Ming Chen , Chih-Hsun Lin
发明人： Chun-Wei Hsu , Teng-Chun Tsai , Chia-Lin Hsu , Po-Cheng Huang , Chia-Hsi Chen , Yen-Ming Chen , Chih-Hsun Lin
IPC分类号： H01L21/306
CPC分类号： H01L21/31053 , H01L21/02065 , H01L21/76224 , H01L29/66545
摘要： A chemical mechanical polishing (CMP) process includes steps of providing a substrate, performing a first polishing step to the substrate with an acidic slurry, and performing a second polishing step to the substrate with a basic slurry after the first polishing step.
摘要翻译：化学机械抛光（CMP）工艺包括以下步骤：提供基材，用酸性浆料对基材进行第一抛光步骤，以及在第一抛光步骤之后用碱性浆料对基材进行第二抛光步骤。

30. 发明授权

US07803702B2 Method for fabricating MOS transistors 有权
标题翻译：制造MOS晶体管的方法
公开(公告)号：US07803702B2
公开(公告)日：2010-09-28
申请号：US12189203
申请日：2008-08-11
申请人： Kuo-Chih Lai , Yi-Wei Chen , Nien-Ting Ho , Teng-Chun Tsai
发明人： Kuo-Chih Lai , Yi-Wei Chen , Nien-Ting Ho , Teng-Chun Tsai
IPC分类号： H01L21/28
CPC分类号： H01L21/28518 , H01L29/165 , H01L29/6659 , H01L29/66636
摘要： A method for fabricating metal-oxide transistors is disclosed. First, a semiconductor substrate having a gate structure is provided, in which the gate structure includes a gate dielectric layer and a gate. A source/drain region is formed in the semiconductor substrate, and a cleaning step is performed to fully remove native oxides from the surface of the semiconductor substrate. An oxidation process is conducted to form an oxide layer on the semiconductor substrate and the oxide layer is then treated with fluorine-containing plasma to form a fluorine-containing layer on the surface of the semiconductor substrate. A metal layer is deposited on the semiconductor substrate thereafter and a thermal treatment is performed to transform the metal layer into a silicide layer.
摘要翻译：公开了一种用于制造金属氧化物晶体管的方法。首先，提供具有栅极结构的半导体衬底，其中栅极结构包括栅极介电层和栅极。在半导体衬底中形成源极/漏极区域，并且执行清洁步骤以从半导体衬底的表面中完全去除天然氧化物。进行氧化处理以在半导体衬底上形成氧化物层，然后用含氟等离子体处理氧化物层，以在半导体衬底的表面上形成含氟层。此后，在半导体衬底上沉积金属层，并进行热处理以将金属层转变成硅化物层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式