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21. 发明授权

US08035165B2 Integrating a first contact structure in a gate last process 有权
标题翻译：在最后一个进程中集成第一个接触结构
公开(公告)号：US08035165B2
公开(公告)日：2011-10-11
申请号：US12341891
申请日：2008-12-22
申请人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66606 , H01L21/823814 , H01L21/823871
摘要： A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.
摘要翻译：提供一种半导体器件，其包括半导体衬底，形成在衬底上的晶体管，晶体管具有包括金属栅极和高k栅极电介质的栅极堆叠以及形成在衬底上的双重第一接触。所述双重第一接触包括第一接触特征，覆盖所述第一接触特征的第二接触特征以及形成在所述第二接触特征的侧壁和底部上的金属屏障，所述金属阻挡层将所述第一接触特征耦合到所述第二接触特征。

22. 发明授权

US07977181B2 Method for gate height control in a gate last process 有权
标题翻译：门最后进程门控高度的方法
公开(公告)号：US07977181B2
公开(公告)日：2011-07-12
申请号：US12420254
申请日：2009-04-08
申请人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang
发明人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823842 , H01L21/28088 , H01L21/823814 , H01L21/82385 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66636
摘要： Provided is a method that includes forming first and second gate structures in first and second regions, respectively, the first gate structure including a first hard mask layer having a first thickness and the second gate structure including a second hard mask layer having a second thickness less than the first thickness, removing the second hard mask layer from the second gate structure, forming an inter-layer dielectric (ILD) over the first and second gate structures, performing a first chemical mechanical polishing (CMP), remove the silicon layer from the second gate structure thereby forming a first trench, forming a first metal layer to fill the first trench, performing a second CMP, remove the remaining portion of the first hard mask layer and the silicon layer from the first gate structure thereby forming a second trench, forming a second metal layer to fill the second trench, and performing a third CMP.
摘要翻译：提供了一种方法，其包括分别在第一和第二区域中形成第一和第二栅极结构，第一栅极结构包括具有第一厚度的第一硬掩模层，第二栅极结构包括具有第二厚度的第二硬掩模层从第二栅极结构去除第二硬掩模层，在第一和第二栅极结构上形成层间电介质（ILD），执行第一化学机械抛光（CMP），将硅层从第二栅极结构，由此形成第一沟槽，形成第一金属层以填充第一沟槽，执行第二CMP，从第一栅极结构移除第一硬掩模层和硅层的剩余部分，从而形成第二沟槽，形成第二金属层以填充第二沟槽，并执行第三CMP。

23. 发明授权

US07919792B2 Standard cell architecture and methods with variable design rules 有权
标题翻译：标准单元结构和具有可变设计规则的方法
公开(公告)号：US07919792B2
公开(公告)日：2011-04-05
申请号：US12338632
申请日：2008-12-18
申请人： Oscar M. K. Law , Manoj Achyutrao Joshi , Kong-Beng Thei , Harry Chuang
发明人： Oscar M. K. Law , Manoj Achyutrao Joshi , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L27/10 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/11807 , H01L27/0207 , H01L2924/0002 , H01L2924/00
摘要： Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed.
摘要翻译：公开了具有层与单元边界间隔的可变规则的标准单元布局的结构和方法。在一个实施例中，第一标准单元布局设置有导电层，其具有间隔最小间隔距离的至少两个部分，所述导电层具有至少一个与单元边界隔开的部分，第一间隔距离小于一半的最小间距; 与所述第一标准单元相邻设置的第二标准单元，所述第二单元中的所述导电层的至少一个第二部分与所述第一标准单元中的所述第一部分相邻设置，并且与所述第一标准单元间隔开第二间隔，最小其中所述第一和第二间距的总和至少与所述最小间隔一样大。公开了一种形成标准的方法。

24. 发明申请

US20100112732A1 NOVEL PROCESS FOR CONTROLLING SHALLOW TRENCH ISOLATION STEP HEIGHT 有权
标题翻译：用于控制SHALLOW TRENCH隔离步骤高度的新方法
公开(公告)号：US20100112732A1
公开(公告)日：2010-05-06
申请号：US12478135
申请日：2009-06-04
申请人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen , Shun-Jang Liao
发明人： Su-Chen Lai , Kong-Beng Thei , Harry Chuang , Gary Shen , Shun-Jang Liao
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L21/76224 , H01L22/12
摘要： A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time.
摘要翻译：公开了一种用于制造隔离区的台阶高度之间的均匀性提高的集成电路的方法。该方法包括提供具有一个或多个沟槽的衬底; 填充一个或多个沟槽; 在所述一个或多个填充的沟槽上执行化学机械抛光，其中所述一个或多个填充的沟槽中的每一个包括厚度; 测量所述一个或多个填充沟槽中的每一个的厚度; 基于所测量的一个或多个填充的沟槽中的每一个的厚度来确定进行蚀刻处理的时间量; 并对所确定的时间量进行蚀刻处理。

25. 发明申请

US20100052070A1 NOVEL DEVICE SCHEME OF HKMG GATE-LAST PROCESS 有权
标题翻译： HKMG GATE-LAST过程的新设备方案
公开(公告)号：US20100052070A1
公开(公告)日：2010-03-04
申请号：US12536878
申请日：2009-08-06
申请人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
发明人： Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/66545
摘要： The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate.
摘要翻译：本公开提供了制造半导体器件的金属栅叠层的方法。该方法包括在半导体衬底上形成高k电介质材料层; 在所述高k电介质材料层上形成导电材料层; 在n型场效应晶体管（nFET）区域中形成伪栅极，在使用多晶硅的pFET区域中形成第二伪栅极; 在所述半导体衬底上形成层间电介质（ILD）材料; 对半导体衬底施加第一化学机械抛光（CMP）工艺; 从第一伪栅极去除多晶硅，产生第一栅极沟槽; 在第一栅极沟槽上形成n型金属; 对所述半导体衬底施加第二CMP工艺; 从第二伪栅极去除多晶硅，产生第二栅极沟槽; 在所述第二栅极沟槽中形成p型金属; 以及对所述半导体衬底施加第三CMP处理。

26. 发明授权

US07632729B2 Method for semiconductor device performance enhancement 有权
标题翻译：半导体器件性能提高的方法
公开(公告)号：US07632729B2
公开(公告)日：2009-12-15
申请号：US11527616
申请日：2006-09-27
申请人： Harry Chuang , Kong-Beng Thei , Chung-Long Cheng , Sheng-Chen Chung , Wen-Huei Guo , Jung-Hui Kao , Ryan Chia-Jen Chen , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Chung-Long Cheng , Sheng-Chen Chung , Wen-Huei Guo , Jung-Hui Kao , Ryan Chia-Jen Chen , Mong-Song Liang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/7843
摘要： A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.
摘要翻译：公开了制造半导体器件的方法。该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。在NMOS和PMOS器件上形成第一绝缘层。在第一绝缘层上形成第二绝缘层。覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。在NMOS和PMOS器件上进行第一次热处理。去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分，并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

27. 发明申请

US20090273052A1 Reducing Device Performance Drift Caused by Large Spacings Between Action Regions 有权
标题翻译：减少行动区域之间大间距引起的设备性能漂移
公开(公告)号：US20090273052A1
公开(公告)日：2009-11-05
申请号：US12175976
申请日：2008-07-18
申请人： Harry Chuang , Kong-Beng Thei , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Mong-Song Liang
IPC分类号： H01L21/322 , H01L27/10
CPC分类号： H01L21/823475 , H01L21/31155 , H01L21/823412 , H01L21/823481 , H01L29/7846
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 以及形成第一和第二MOS器件。第一MOS器件包括半导体衬底中的第一有源区; 和第一个主动区域的第一个门。第二MOS器件包括半导体衬底中的第二有源区; 以及在第二活动区域上的第二栅极。该方法还包括在第一和第二有源区之间形成电介质区域，其中电介质区域具有固有应力; 以及注入所述电介质区域以在所述电介质区域中形成应力释放区域，其中所述第一和第二MOS器件的源极和漏极区域在植入步骤期间不被植入。

28. 发明授权

US07612364B2 MOS devices with source/drain regions having stressed regions and non-stressed regions 有权
标题翻译：源极/漏极区域具有应力区域和非应力区域的MOS器件
公开(公告)号：US07612364B2
公开(公告)日：2009-11-03
申请号：US11602100
申请日：2006-11-20
申请人： Harry Chuang , Kong-Beng Thei , Yuan-Chen Sun
发明人： Harry Chuang , Kong-Beng Thei , Yuan-Chen Sun
IPC分类号： H01L29/06
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the stressor comprises an impurity of a first conductivity type; and a portion of the semiconductor substrate adjoining the stressor and on an opposite side of the stressor from the gate stack, wherein the portion of the semiconductor substrate is doped with an impurity of the first conductivity type.
摘要翻译：半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; 应力源，其具有至少一部分在所述半导体衬底中并且邻近所述栅叠层，其中所述应力源包括第一导电类型的杂质; 所述半导体衬底的与所述应力源相邻的部分以及所述应力源与所述栅极堆叠相反的一侧，其中所述半导体衬底的所述部分掺杂有所述第一导电类型的杂质。

29. 发明申请

US20090218623A1 SOI DEVICES AND METHODS FOR FABRICATING THE SAME 有权
公开(公告)号：US20090218623A1
公开(公告)日：2009-09-03
申请号：US12468137
申请日：2009-05-19
申请人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
发明人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/4238 , H01L29/78636
摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.

30. 发明授权

US07550795B2 SOI devices and methods for fabricating the same 有权
标题翻译： SOI器件及其制造方法
公开(公告)号：US07550795B2
公开(公告)日：2009-06-23
申请号：US11477953
申请日：2006-06-30
申请人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
发明人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
IPC分类号： H01L29/76
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/4238 , H01L29/78636
摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.
摘要翻译：提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。在衬底上形成第一绝缘层。在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。第一电介质层形成在每个半导体岛的一部分上。导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

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