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21. 发明授权

US08460960B2 Method for fabricating integrated circuit 有权
标题翻译：集成电路制造方法
公开(公告)号：US08460960B2
公开(公告)日：2013-06-11
申请号：US13186607
申请日：2011-07-20
申请人： Meng-Jia Lin , Bang-Chiang Lan , Ming-I Wang , Chien-Hsin Huang
发明人： Meng-Jia Lin , Bang-Chiang Lan , Ming-I Wang , Chien-Hsin Huang
IPC分类号： H01L21/00
CPC分类号： H01L21/31144 , B81C1/00246 , B81C2203/0714 , H01L27/0617
摘要： A method for fabricating integrated circuit is provided. First, a first interconnect structure including a plurality of first dielectric layers and a plurality of first conductive patterns stacked therewith alternately is formed on a MEMS region of a conductive substrate. Next, an interlayer is formed on the first interconnect structure and covering the first conductive patterns. Next, a poly silicon mask layer corresponding to the first conductive patterns is formed on the interlayer and exposing a portion of the media layer. Next, the portion of the interlayer exposed by the poly silicon mask layer and a portion of the first dielectric layer corresponding thereto are removed to form a plurality of openings. Then, a portion of the conductive substrate in the MEMS region is removed.
摘要翻译：提供一种用于制造集成电路的方法。首先，在导电基板的MEMS区域上形成包括多个第一电介质层和交替堆叠的多个第一导电图案的第一互连结构。接下来，在第一互连结构上形成中间层并覆盖第一导电图案。接下来，在中间层上形成对应于第一导电图案的多晶硅掩模层，并暴露介质层的一部分。接下来，去除由多晶硅掩模层暴露的层的部分和与其对应的第一介电层的一部分，以形成多个开口。然后，去除MEMS区域中的导电衬底的一部分。

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