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21. 发明授权

US07357838B2 Relaxed silicon germanium substrate with low defect density 有权
标题翻译：具有低缺陷密度的松弛硅锗衬底
公开(公告)号：US07357838B2
公开(公告)日：2008-04-15
申请号：US11074738
申请日：2005-03-08
申请人： Chun Chieh Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
发明人： Chun Chieh Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
IPC分类号： C30B23/00
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/324
摘要： A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe is provided.
摘要翻译：提供了在松弛的低缺陷密度半导体合金层（例如SiGe）上形成应变硅层的方法。

22. 发明授权

US06867433B2 Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors 有权
标题翻译：包含应变通道部分耗尽，完全耗尽和多栅极晶体管的绝缘体上半导体芯片
公开(公告)号：US06867433B2
公开(公告)日：2005-03-15
申请号：US10426566
申请日：2003-04-30
申请人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
发明人： Yee-Chia Yeo , How-Yu Chen , Chien-Chao Huang , Wen-Chin Lee , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/66795 , H01L29/7842 , H01L29/7843 , H01L29/7854
摘要： In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.
摘要翻译：根据本发明的优选实施例，绝缘体上硅（SOI）芯片包括覆盖在绝缘体层上的预定厚度的硅层。在硅层的第一部分上形成包括应变沟道区的多栅极全耗尽SOI MOSFET。包括形成在硅层的另一部分上的应变沟道区的平面SOI MOSFET。例如，平面SOI MOSFET可以是平面全耗尽SOI（FD-SOI）MOSFET，或者平面SOI MOSFET可以是平面部分耗尽的SOI（PD-SOI）MOSFET。

23. 发明授权

US07342289B2 Strained silicon MOS devices 有权
标题翻译：应变硅MOS器件
公开(公告)号：US07342289B2
公开(公告)日：2008-03-11
申请号：US10637351
申请日：2003-08-08
申请人： Chien-Chao Huang , Chung-Hu Ge , Wen-Chin Lee , Chenming Hu , Carlos H. Diaz , Fu-Liang Yang
发明人： Chien-Chao Huang , Chung-Hu Ge , Wen-Chin Lee , Chenming Hu , Carlos H. Diaz , Fu-Liang Yang
IPC分类号： H01L29/76
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7842 , H01L29/7843
摘要： A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.
摘要翻译：一种提高集成电路中MOS器件的载流子迁移率的结构。该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

24. 发明申请

US20070278541A1 Spacer engineering on CMOS devices 审中-公开
标题翻译： CMOS器件上的间隔工程
公开(公告)号：US20070278541A1
公开(公告)日：2007-12-06
申请号：US11446912
申请日：2006-06-05
申请人： Chien-Chao Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/1083 , H01L29/6656 , H01L29/7842
摘要： A MOS device having a reduced LDD dopant diffusion length and a method for forming the same are provided. The MOS device includes a gate stack over a semiconductor substrate, a spacer liner on a sidewall of the gate stack and having a portion over the semiconductor substrate, and a spacer over the spacer liner. The spacer for a PMOS device preferably has a tensile stress, and the spacer for an NMOS device preferably has a compressive stress.
摘要翻译：提供具有降低的LDD掺杂剂扩散长度的MOS器件及其形成方法。 MOS器件包括在半导体衬底上的栅极堆叠，在栅极堆叠的侧壁上的间隔衬垫，并且具有半导体衬底上的部分，以及间隔衬垫上的间隔物。用于PMOS器件的间隔物优选具有拉伸应力，并且用于NMOS器件的间隔物优选地具有压应力。

25. 发明申请

US20070222035A1 Stress intermedium engineering 审中-公开
标题翻译：应力中介工程
公开(公告)号：US20070222035A1
公开(公告)日：2007-09-27
申请号：US11387601
申请日：2006-03-23
申请人： Chien-Chao Huang , Fu-Liang Yang
发明人： Chien-Chao Huang , Fu-Liang Yang
IPC分类号： H01L29/06
CPC分类号： H01L29/78 , H01L29/7843 , H01L29/7845
摘要： Embodiments of the invention provide structures and methods for forming a strained MOS transistor. A stressor layer is formed over the transistor. Embodiments include an intermedium layer between the stressor layer and a portion of the transistor. In an embodiment, the intermedium comprises a layer formed between the stressor layer and the gate electrode sidewall spacers. In another embodiment, the intermedium comprises a silicided portion of the substrate formed over the LDS/LDD regions. A transistor that includes the intermedium and, stressor layer has a vertically oriented stress within the channel region. The vertically oriented stress is tensile in a PMOS transistor and compressive in an NMOS transistor.
摘要翻译：本发明的实施例提供了用于形成应变MOS晶体管的结构和方法。在晶体管上方形成应力层。实施例包括应力层与晶体管的一部分之间的中间层。在一个实施例中，中间层包括在应力层和栅电极侧壁间隔件之间形成的层。在另一个实施例中，中间层包括在LDS / LDD区上形成的衬底的硅化物部分。包括中间层和应力层的晶体管在沟道区域内具有垂直取向的应力。垂直取向的应力是PMOS晶体管中的拉伸和NMOS晶体管中的压缩。

26. 发明授权

US07183137B2 Method for dicing semiconductor wafers 有权
标题翻译：切割半导体晶片的方法
公开(公告)号：US07183137B2
公开(公告)日：2007-02-27
申请号：US10725697
申请日：2003-12-01
申请人： Hsin-Hui Lee , Chien-Chao Huang , Chao-Hsiung Wang , Fu-Liang Yang , Chenming Hu
发明人： Hsin-Hui Lee , Chien-Chao Huang , Chao-Hsiung Wang , Fu-Liang Yang , Chenming Hu
IPC分类号： H01L21/50 , H01L21/78
CPC分类号： H01L21/78 , B28D5/00
摘要： A method is disclosed for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure.
摘要翻译：公开了一种用于切割具有金刚石结构的基底材料的晶片的方法。晶片首先进行抛光处理，其中将晶片的预定部分从其背面抛光。然后将晶片沿着与金刚石结构的天然裂解方向成预定偏移角的方向通过至少一条线切割。

27. 发明申请

US20060202237A1 Metal gate semiconductor device and manufacturing method 有权
标题翻译：金属栅极半导体器件及其制造方法
公开(公告)号：US20060202237A1
公开(公告)日：2006-09-14
申请号：US11400853
申请日：2006-04-10
申请人： Chien-Chao Huang , Kuang-Hsin Chen , Fu-Liang Yang
发明人： Chien-Chao Huang , Kuang-Hsin Chen , Fu-Liang Yang
IPC分类号： H01L29/768
CPC分类号： H01L29/66553 , H01L21/28097 , H01L21/82345 , H01L21/823468 , H01L29/665 , H01L29/66507 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： A method for manufacturing a metal gate includes providing a substrate including a gate electrode located on the substrate. A plurality of layers is formed, including a first layer located on the substrate and the gate electrode and a second layer adjacent the first layer. The layers are etched to form a plurality of adjacent spacers, including a first spacer located on the substrate and adjacent the gate electrode and a second spacer adjacent the first spacer. The first spacer is then etched and a metal layer is formed on the device immediately adjacent to the gate electrode. The metal layer is then reacted with the gate electrode to form a metal gate.
摘要翻译：一种用于制造金属栅极的方法包括提供包括位于基板上的栅电极的基板。形成多个层，包括位于衬底上的第一层和栅电极以及与第一层相邻的第二层。这些层被蚀刻以形成多个相邻的间隔物，包括位于衬底上并且邻近栅电极的第一间隔物和邻近第一间隔物的第二间隔物。然后蚀刻第一间隔物，并且在紧邻栅电极的器件上形成金属层。然后金属层与栅电极反应形成金属栅极。

28. 发明授权

US06878610B1 Relaxed silicon germanium substrate with low defect density 有权
标题翻译：具有低缺陷密度的松弛硅锗衬底
公开(公告)号：US06878610B1
公开(公告)日：2005-04-12
申请号：US10228545
申请日：2002-08-27
申请人： Chun Chich Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
发明人： Chun Chich Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
IPC分类号： C30B1/00 , H01L21/00 , H01L21/20 , H01L21/205 , H01L21/324 , H01L21/36 , H01L21/84 , H01L29/10
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/324
摘要： A method of forming a strained silicon layer on a relaxed, low defect density semiconductor alloy layer such as SiGe, has been developed. In a first embodiment of this invention the relaxed, low density SiGe layer is epitaxially grown on an silicon layer which in turn is located on an underlying SiGe layer. During the epitaxial growth of the overlying SiGe layer defects are formed in the underlying silicon layer resulting in the desired, relaxation, and decreased defect density for the SiGe layer. A second embodiment features an anneal procedure performed during growth of the relaxed SiGe layer, resulting in additional relaxation and decreased defect density, while a third embodiment features an anneal procedure performed to the underlying silicon layer prior to epitaxial growth of the relaxed SiGe layer, again allowing optimized relaxation and defect density to be realized for the SiGe layer. The ability to obtain a strained silicon layer on a relaxed, low defect density SiGe layer, allows devices with enhanced carrier mobility to be formed in the surface of the strained silicon layer, with decreased risk of leakage due the presence of the underlying, relaxed, low defect density SiGe layer.
摘要翻译：已经开发了在松弛的低缺陷密度半导体合金层如SiGe上形成应变硅层的方法。在本发明的第一实施例中，松散的低密度SiGe层在硅层上外延生长，硅层又位于下面的SiGe层上。在覆盖SiGe层的外延生长期间，在下层硅层中形成缺陷，导致SiGe层所需的，松弛的和降低的缺陷密度。第二个实施例的特征在于在松弛的SiGe层的生长期间执行的退火程序，导致附加的松弛和降低的缺陷密度，而第三实施例的特征在于在弛豫的SiGe层的外延生长之前对下面的硅层进行退火处理允许为SiGe层实现优化的弛豫和缺陷密度。在松弛的低缺陷密度SiGe层上获得应变硅层的能力允许在应变硅层的表面形成具有增强的载流子迁移率的器件，由于存在下面的，放松的，低缺陷密度SiGe层。

29. 发明授权

US08564018B2 Relaxed silicon germanium substrate with low defect density 有权
标题翻译：具有低缺陷密度的松弛硅锗衬底
公开(公告)号：US08564018B2
公开(公告)日：2013-10-22
申请号：US12038091
申请日：2008-02-27
申请人： Chun Chich Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
发明人： Chun Chich Lin , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
IPC分类号： H01L21/02
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/324
摘要： A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.
摘要翻译：公开了一种用于集成电路的结构。该结构包括晶体衬底和四个结晶层。第一晶格常数的第一晶体层位于晶体衬底上。第二晶体层具有不同于第一晶格常数的第二晶格常数，并且位于所述第一晶体层上。第三晶体层具有与所述第二晶格常数不同的第三晶格常数，并且位于所述第二晶体层上。应变的第四晶体层至少部分地包括MOSFET器件。

30. 发明申请

US20080142842A1 RELAXED SILICON GERMANIUM SUBSTRATE WITH LOW DEFECT DENSITY 有权
标题翻译：具有低缺陷密度的松弛硅锗基板
公开(公告)号：US20080142842A1
公开(公告)日：2008-06-19
申请号：US12038091
申请日：2008-02-27
申请人： Chun Chich LIN , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
发明人： Chun Chich LIN , Yee-Chia Yeo , Chien-Chao Huang , Chao-Hsiung Wang , Tien-Chih Chang , Chenming Hu , Fu-Liang Yang , Shih-Chang Chen , Mong-Song Liang , Liang-Gi Yao
IPC分类号： H01L29/04
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02505 , H01L21/02532 , H01L21/324
摘要： A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.
摘要翻译：公开了一种用于集成电路的结构。该结构包括晶体衬底和四个结晶层。第一晶格常数的第一晶体层位于晶体衬底上。第二晶体层具有不同于第一晶格常数的第二晶格常数，并且位于所述第一晶体层上。第三晶体层具有与所述第二晶格常数不同的第三晶格常数，并且位于所述第二晶体层上。应变的第四晶体层至少部分地包括MOSFET器件。

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