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21. 发明授权

US06759750B2 Method for integrating low-K materials in semiconductor fabrication 失效
标题翻译：半导体制造中低K材料的集成方法
公开(公告)号：US06759750B2
公开(公告)日：2004-07-06
申请号：US10623910
申请日：2003-07-18
申请人： Shau-Lin Shue , Ming-Hsing Tsai
发明人： Shau-Lin Shue , Ming-Hsing Tsai
IPC分类号： H01L2348
CPC分类号： H01L23/522 , H01L21/76801 , H01L21/76807 , H01L2924/0002 , H01L2924/00
摘要： A method for integrating low-K materials in semiconductor fabrication. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer comprising an organic low-K material. The dielectric layer is patterned to form pillar openings. A pillar layer is deposited over the semiconductor structure; thereby filling the pillar openings with the pillar layer. The pillar layer is planarized to form pillars embedded in said dielectric layer. The pillar layer comprises a material having good thermal stability, good structural strength, and good bondability of spin coating back-end materials, improving the manufacturability of organic, low-K dielectrics in semiconductor fabrication. In one embodiment, the pillars are formed prior to forming dual damascene interlayer contacts. In another embodiment, pillars are formed simultaneously with interlayer contacts.
摘要翻译：一种用于在半导体制造中集成低K材料的方法。该方法开始于提供其上具有介电层的半导体结构，其中介电层包含有机低K材料。图案化电介质层以形成柱状开口。在半导体结构上沉积柱层; 从而用柱层填充柱状开口。柱层被平坦化以形成嵌入在所述介电层中的柱。柱层包括具有良好的热稳定性，良好的结构强度和旋涂后端材料的良好的粘合性的材料，提高半导体制造中的有机，低K电介质的可制造性。在一个实施例中，在形成双镶嵌层间接触之前形成柱。在另一个实施方案中，柱与层间接触同时形成。

22. 发明授权

US06562725B2 Dual damascene structure employing nitrogenated silicon carbide and non-nitrogenated silicon carbide etch stop layers 有权
标题翻译：采用氮化碳化硅和非氮化碳化硅蚀刻停止层的双镶嵌结构
公开(公告)号：US06562725B2
公开(公告)日：2003-05-13
申请号：US09899420
申请日：2001-07-05
申请人： Ming-Hsing Tsai , Ching-Hua Hsieh , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Ching-Hua Hsieh , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L2100
CPC分类号： H01L21/76829 , H01L21/31116 , H01L21/314 , H01L21/7681 , H01L21/76834
摘要： Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed a first etch stop layer formed of a first material and a second etch stop layer formed of a second material. One of the first material and the second material is a non-nitrogenated silicon carbide material and the other of the first material and the second material is a nitrogenated silicon carbide material. By employing the first material and the second material, there may be etched completely through the first etch stop layer to reach a contact region formed there beneath while not etching completely through the second etch stop layer to reach a first dielectric layer formed there beneath.
摘要翻译：在用于在微电子制造中形成双镶嵌孔的双镶嵌方法中，采用由第一材料形成的第一蚀刻停止层和由第二材料形成的第二蚀刻停止层。第一材料和第二材料之一是非氮化碳化硅材料，第一材料和第二材料中的另一种是氮化碳化硅材料。通过使用第一材料和第二材料，可以完全蚀刻通过第一蚀刻停止层以到达其下方形成的接触区域，而不完全蚀刻通过第二蚀刻停止层，以到达在其下方形成的第一介电层。

23. 发明授权

US06479389B1 Method of doping copper metallization 有权
标题翻译：掺杂铜金属化方法
公开(公告)号：US06479389B1
公开(公告)日：2002-11-12
申请号：US09412632
申请日：1999-10-04
申请人： Ming-Hsing Tsai , Sheng Hsiang Chen
发明人： Ming-Hsing Tsai , Sheng Hsiang Chen
IPC分类号： H01L21302
CPC分类号： H01L21/76877 , H01L21/76886
摘要： This invention describes two new methods to form copper alloy films. In the first embodiment of this invention physical vapor deposition (PVD) or sputtering of a copper alloy film, is then followed by a chemical vapor deposition (CVD) or electro-chemical deposition (ECD) of a layer of pure copper. In the second embodiment of this invention chemical vapor deposition (CVD) or electro-chemical deposition (ECD) deposits a layer of pure copper, which is then followed by physical vapor deposition (PVD) or sputtering of a copper alloy film. In yet another embodiment to these methods, special, separate low temperature annealing steps follow said methods to enhance copper alloy formation. By the two deposition techniques briefly described above, high aspect ratio vias and trenches can be filled with copper corrosion and electromigration resistant alloys.
摘要翻译：本发明描述了形成铜合金膜的两种新方法。在本发明的第一实施例中，铜合金膜的物理气相沉积（PVD）或溅射之后是纯铜层的化学气相沉积（CVD）或电化学沉积（ECD）。在本发明的第二实施例中，化学气相沉积（CVD）或电化学沉积（ECD）沉积一层纯铜，然后进行物理气相沉积（PVD）或铜合金膜的溅射。在这些方法的另一个实施方案中，特殊的分开的低温退火步骤遵循所述方法以增强铜合金的形成。通过上述两种沉积技术，可以用铜腐蚀和电迁移合金填充高纵横比通孔和沟槽。

24. 发明授权

US06420258B1 Selective growth of copper for advanced metallization 有权
标题翻译：铜的选择性增长用于高级金属化
公开(公告)号：US06420258B1
公开(公告)日：2002-07-16
申请号：US09434564
申请日：1999-11-12
申请人： Sheng Hsiung Chen , Ming-Hsing Tsai
发明人： Sheng Hsiung Chen , Ming-Hsing Tsai
IPC分类号： H01L214763
CPC分类号： H01L21/76879
摘要： A novel and improved method of fabricating an integrated circuit, in which special copper films are formed by a combination of physical vapor deposition (PVD), chemical mechanical polish (CMP) and electrochemical copper deposition (ECD) techniques. The methods of the present invention make efficient use of several process steps resulting in less processing time, lower costs and higher device reliability. By these techniques, high aspect ratio trenches can be filled with copper without the problem of dishing. A special, selective electrochemical deposition (ECD) of copper metal is utilized taking place only on the seed layer in the trench. This auto-plating or “plate-up” occurs only in the trench and provides good sealing around the trench perimeter and fine copper metal coverage of the trench for subsequent robust interconnects. The selective plating of copper provides a robust copper film that is easily removed by subsequent chemical mechanical polish (CMP) and tends to be more uniform and free of the usual defects associated with CMP films.
摘要翻译：一种新颖且改进的制造集成电路的方法，其中通过物理气相沉积（PVD），化学机械抛光（CMP）和电化学铜沉积（ECD）技术的组合形成特殊的铜膜。本发明的方法有效地利用几个工艺步骤，导致更少的处理时间，更低的成本和更高的器件可靠性。通过这些技术，可以用铜填充高纵横比沟槽，而不会出现凹陷的问题。仅在沟槽中的种子层上使用铜金属的特殊的选择性电化学沉积（ECD）。这种自动电镀或“平板化”仅发生在沟槽中，并且在沟槽周边和沟槽的细铜金属覆盖层周围提供良好的密封以用于随后的鲁棒互连。铜的选择性电镀提供了坚固的铜膜，其易于通过后续的化学机械抛光（CMP）去除，并且趋向于更均匀并且没有与CMP膜相关的常见缺陷。

25. 发明授权

US06224737B1 Method for improvement of gap filling capability of electrochemical deposition of copper 有权
标题翻译：改进铜电化学沉积间隙填充能力的方法
公开(公告)号：US06224737B1
公开(公告)日：2001-05-01
申请号：US09377540
申请日：1999-08-19
申请人： Ming-Hsing Tsai , Wen-Jye Tsai , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Wen-Jye Tsai , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： C25D502
CPC分类号： H01L21/76877 , C25D3/38 , C25D5/48 , C25D7/123 , H01L21/2885 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure having a trench formed therein is provided. The semiconductor structure may be a substrate with an overlying interlevel metal dielectric layer having the trench. A voltage is applied to the trenched semiconductor inducing a bias field where there is a first field proximate the trench bottom and a second field, greater than the first field, proximate the trench's upper side walls and the semiconductor upper surface proximate the trench. The semiconductor structure is placed into an electroplating solution containing a predetermined concentration of brighteners and levelers. Because of the induced bias field, the brightener concentration is greater proximate the trench bottom and the leveler concentration is greater the trench's upper side walls and the semiconductor upper surface proximate the trench. A copper layer having a predetermined thickness is then electrolytically deposited within the trench in a “bottom-up” fashion and blanket fills the upper surface of the semiconductor structure. The structure may then be planarized by CMP to create a planarized copper filled trench.
摘要翻译：提供具有形成在其中的沟槽的半导体结构。半导体结构可以是具有具有沟槽的上覆层间金属介电层的衬底。电压被施加到沟槽半导体，其诱导偏置场，其中存在靠近沟槽底部的第一场和大于第一场，接近沟槽的上侧壁和靠近沟槽的半导体上表面的第二场。将半导体结构放入含有预定浓度的增白剂和矫直剂的电镀溶液中。由于感应偏压场，光滑剂浓度在沟槽底部附近较大，并且矫直剂浓度大于沟槽的上侧壁和接近沟槽的半导体上表面。然后将具有预定厚度的铜层以“自下而上”的方式电解沉积在沟槽内，并且覆盖填充半导体结构的上表面。然后可以通过CMP平面化该结构以产生平坦化的铜填充沟槽。

26. 发明授权

US6133144A Self aligned dual damascene process and structure with low parasitic capacitance 有权
标题翻译：自对准双镶嵌工艺和结构具有低寄生电容
公开(公告)号：US6133144A
公开(公告)日：2000-10-17
申请号：US368864
申请日：1999-08-06
申请人： Ming-Hsing Tsai , Shau-Lin Shue
发明人： Ming-Hsing Tsai , Shau-Lin Shue
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/7681
摘要： An improved and novel process for fabricating unique interconnect conducting lines and via contact structures has been developed. Using this special self aligned dual damascene process, special interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of double etch stop or etch barrier layers. The key process step of this invention is special patterning of the etch stop or etch barrier layer. This is the advantage of this invention over Prior Art processes that need a continuous, thick stop layer that has a etching selectivity to silicon dioxide, SiO.sub.2 (increasing parasitic capacitance). However, in this invention a self aligned dual damascene process and structure is presented that is easier to process and has low parasitic capacitance. Repeating the self aligned dual damascene processing steps, constructs multilevel conducting structures. This process reduces processing time, reduces the cost of ownership, (compatible with low dielectric constant materials) and at the same time produces a product with superior lines and via contact structures (by use of special etch stop or etch barrier layer patterning), hence improving reliability.
摘要翻译：已经开发了用于制造独特的互连导线和通孔接触结构的改进和新颖的工艺。使用这种特殊的自对准双镶嵌工艺，形成了具有低寄生电容（低RC时间常数）的特殊互连导线和通孔触点。本发明包括使用双蚀刻停止层或蚀刻阻挡层。本发明的关键工艺步骤是蚀刻停止或蚀刻阻挡层的特殊图案化。这是本发明优于现有技术方法的优点，其需要具有对二氧化硅，SiO 2（增加寄生电容）的蚀刻选择性的连续的厚的停止层。然而，在本发明中，提出了一种易于处理并具有低寄生电容的自对准双镶嵌工艺和结构。重复自对准双镶嵌加工步骤，构建多层导电结构。这个过程减少了处理时间，降低了所有权成本（与低介电常数材料兼容），同时产生了具有优异线条和通孔接触结构的产品（通过使用特殊的蚀刻阻挡层或蚀刻阻挡层图案），因此提高可靠性。

27. 发明授权

US08053892B2 Low resistance and reliable copper interconnects by variable doping 有权
标题翻译：低电阻和可靠的铜互连可变掺杂
公开(公告)号：US08053892B2
公开(公告)日：2011-11-08
申请号：US11341827
申请日：2006-01-27
申请人： Ting-Chu Ko , Ming-Hsing Tsai , Chien-Hsueh Shih
发明人： Ting-Chu Ko , Ming-Hsing Tsai , Chien-Hsueh Shih
IPC分类号： H01L23/48
CPC分类号： H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.
摘要翻译：提供了一种方法和系统，用于有效地改变半导体器件的金属互连的组成。根据本公开的金属互连在电介质材料上具有中间层，中间层与主金属一起具有较高浓度的杂质金属，杂质金属具有比初级金属低的还原电位。金属互连件在中间层的顶部具有金属合金互连的主层，被中间层包围，主层具有比中间层更高的一次金属浓度，其中，中间层和中间层的中间层和主要层金属合金互连件均保持材料均匀性。

28. 发明申请

US20060276027A1 Interconnects with harmonized stress and methods for fabricating the same 失效
公开(公告)号：US20060276027A1
公开(公告)日：2006-12-07
申请号：US11144742
申请日：2005-06-06
申请人： Yung-Cheng Lu , Ming-Hsing Tsai
发明人： Yung-Cheng Lu , Ming-Hsing Tsai
IPC分类号： H01L21/4763 , H01L23/52
CPC分类号： H01L21/76801 , H01L21/76807 , H01L21/76829 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Interconnects with harmonized stress and methods for fabricating the same. An interconnect comprises a substrate having a conductive member. A composite low-k dielectric layer interposed with at least one stress-harmonizing layer therein overlies the substrate. A conductive feature in the composite low-k dielectric layer passes through the at least one stress-harmonizing layer to electrically connect the conductive member.

29. 发明申请

US20050170648A1 Method to solve via poisoning for porous low-k dielectric 有权
公开(公告)号：US20050170648A1
公开(公告)日：2005-08-04
申请号：US11056758
申请日：2005-02-11
申请人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
发明人： Ming-Hsing Tsai , Jing-Cheng Lin , Shau-Lin Shue , Chen-Hua Yu
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76844 , H01L21/76807 , H01L21/76831 , H01L2221/1063
摘要： A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

30. 发明授权

US06793797B2 Method for integrating an electrodeposition and electro-mechanical polishing process 失效
标题翻译：整合电沉积和机电抛光工艺的方法
公开(公告)号：US06793797B2
公开(公告)日：2004-09-21
申请号：US10106733
申请日：2002-03-26
申请人： Shih-Wei Chou , Ming-Hsing Tsai , Winston Shue , Mong-Song Liang
发明人： Shih-Wei Chou , Ming-Hsing Tsai , Winston Shue , Mong-Song Liang
IPC分类号： C25D518
CPC分类号： H01L21/2885 , B23H5/08 , C25D5/18 , C25D7/123 , H01L21/32125 , H01L21/76877
摘要： A method for alternately electrodepositing and electro-mechanically polishing to selectively fill a semiconductor feature with metal including a) providing an anode assembly and a semiconductor wafer disposed in spaced apart relation including an electrolyte there between the semiconductor wafer including a process surface including anisotropically etched features arranged for an electrodeposition process; b) applying an electric potential across the anode assembly and the semiconductor wafer to induce an electrolyte flow at a first current density to electrodeposit a metal filling portion onto the process surface; c) reversing the electric potential to reverse the electrolyte flow at a second current density to electropolish the process surface in an electropolishing process; and, d) sequentially repeating the steps b and c to electrodeposit at least a second metal filling portion to substantially fill the anisotropically etched features.
摘要翻译：一种用于交替电沉积和电机械抛光以选择性地用金属填充半导体特征的方法，包括：a）提供以间隔开的关系设置的阳极组件和半导体晶片，所述阳极组件和半导体晶片在半导体晶片之间包括电解质，所述电解质包括包括各向异性蚀刻特征安排电沉积过程; b）在阳极组件和半导体晶片之间施加电位以在第一电流密度下引起电解质流动，以将金属填充部分电沉积到工艺表面上; c）逆转电位以在第二电流密度下反转电解质流动，以在电抛光过程中电镀处理表面; 以及d）依次重复步骤b和c以电沉积至少第二金属填充部分以基本上填充各向异性蚀刻的特征。

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