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21. 发明授权

US07910994B2 System and method for source/drain contact processing 有权
标题翻译：源/漏接触处理的系统和方法
公开(公告)号：US07910994B2
公开(公告)日：2011-03-22
申请号：US11872546
申请日：2007-10-15
申请人： Chen-Hua Yu , Cheng-Hung Chang , Chen-Nan Yeh , Yu-Rung Hsu
发明人： Chen-Hua Yu , Cheng-Hung Chang , Chen-Nan Yeh , Yu-Rung Hsu
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/785 , H01L21/76897 , H01L23/485 , H01L29/20 , H01L29/41791 , H01L29/66795 , H01L29/7843 , H01L2029/7858
摘要： System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.
摘要翻译：公开了用于降低接触电阻并防止由于接触不对准引起的变化的系统和方法。优选实施例包括具有位于鳍内的源/漏区的非平面晶体管。层间电介质覆盖非平面晶体管，并且通过层间电介质将触点形成到源/漏区。接触件优选地与翅片的多个表面接触，以增加接触件和翅片之间的接触面积。

22. 发明授权

US07902035B2 Semiconductor device having multiple fin heights 有权
标题翻译：具有多个翅片高度的半导体器件
公开(公告)号：US07902035B2
公开(公告)日：2011-03-08
申请号：US12484911
申请日：2009-06-15
申请人： Chen-Hua Yu , Chen-Nan Yeh , Yu-Rung Hsu
发明人： Chen-Hua Yu , Chen-Nan Yeh , Yu-Rung Hsu
IPC分类号： H01L21/76
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.
摘要翻译：提供具有多个翅片高度的半导体器件。通过使用多个掩模来在形成在衬底中的沟槽内凹入电介质层来提供多个翅片高度。在另一个实施例中，使用植入模具或电子束光刻来形成光致抗蚀剂材料中的沟槽图案。随后的蚀刻步骤在下面的衬底中形成对应的沟槽。在另一个实施例中，使用多个掩模层来分别蚀刻不同高度的沟槽。可以沿着沟槽的底部形成电介质区域，以通过执行离子注入和随后的退火来隔离散热片。

23. 发明授权

US07612405B2 Fabrication of FinFETs with multiple fin heights 有权
标题翻译：具有多个翅片高度的FinFET的制造
公开(公告)号：US07612405B2
公开(公告)日：2009-11-03
申请号：US11714644
申请日：2007-03-06
申请人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rung Hsu
发明人： Chen-Hua Yu , Chen-Nan Yeh , Chu-Yun Fu , Yu-Rung Hsu
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L29/66795
摘要： A semiconductor structure includes a first semiconductor strip extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the first semiconductor strip has a first height. A first insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the first semiconductor strip, wherein the first insulating region has a first top surface lower than a top surface of the first semiconductor strip. A second semiconductor strip extends from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the second semiconductor strip has a second height greater than the first height. A second insulating region is formed in the semiconductor substrate and surrounding a bottom portion of the second semiconductor strip, wherein the second insulating region has a second top surface lower than the first top surface, and wherein the first and the second insulating regions have substantially same thicknesses.
摘要翻译：半导体结构包括从半导体衬底的顶表面延伸到半导体衬底中的第一半导体条，其中第一半导体条具有第一高度。第一绝缘区域形成在半导体衬底中并围绕第一半导体条的底部，其中第一绝缘区具有比第一半导体条的顶表面低的第一顶表面。第二半导体条从半导体衬底的顶表面延伸到半导体衬底中，其中第二半导体条的第二高度大于第一高度。第二绝缘区域形成在半导体衬底中并围绕第二半导体条的底部，其中第二绝缘区域具有比第一顶表面低的第二顶表面，并且其中第一绝缘区域和第二绝缘区域基本相同厚度

24. 发明申请

US20090096002A1 System and Method for Source/Drain Contact Processing 有权
标题翻译：源/排水接触处理系统和方法
公开(公告)号：US20090096002A1
公开(公告)日：2009-04-16
申请号：US11872546
申请日：2007-10-15
申请人： Chen-Hua Yu , Cheng-Hung Chang , Chen-Nan Yeh , Yu-Rung Hsu
发明人： Chen-Hua Yu , Cheng-Hung Chang , Chen-Nan Yeh , Yu-Rung Hsu
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/76897 , H01L23/485 , H01L29/20 , H01L29/41791 , H01L29/66795 , H01L29/7843 , H01L2029/7858
摘要： System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.
摘要翻译：公开了用于降低接触电阻并防止由于接触不对准引起的变化的系统和方法。优选实施例包括具有位于鳍内的源/漏区的非平面晶体管。层间电介质覆盖非平面晶体管，并且通过层间电介质将触点形成到源/漏区。接触件优选地与翅片的多个表面接触，以增加接触件和翅片之间的接触面积。

25. 发明申请

US20080265338A1 Semiconductor Device Having Multiple Fin Heights 有权
标题翻译：具有多个翅片高度的半导体器件
公开(公告)号：US20080265338A1
公开(公告)日：2008-10-30
申请号：US11741580
申请日：2007-04-27
申请人： Chen-Hua Yu , Chen-Nan Yeh , Yu-Rung Hsu
发明人： Chen-Hua Yu , Chen-Nan Yeh , Yu-Rung Hsu
IPC分类号： H01L29/78
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A semiconductor device having multiple fin heights is provided. Multiple fin heights are provided by using multiple masks to recess a dielectric layer within a trench formed in a substrate. In another embodiment, an implant mold or e-beam lithography are utilized to form a pattern of trenches in a photoresist material. Subsequent etching steps form corresponding trenches in the underlying substrate. In yet another embodiment, multiple masking layers are used to etch trenches of different heights separately. A dielectric region may be formed along the bottom of the trenches to isolate the fins by performing an ion implant and a subsequent anneal.
摘要翻译：提供具有多个翅片高度的半导体器件。通过使用多个掩模来在形成在衬底中的沟槽内凹入电介质层来提供多个翅片高度。在另一个实施例中，使用植入模具或电子束光刻来形成光致抗蚀剂材料中的沟槽图案。随后的蚀刻步骤在下面的衬底中形成对应的沟槽。在另一个实施例中，使用多个掩模层来分别蚀刻不同高度的沟槽。可以沿着沟槽的底部形成电介质区域，以通过执行离子注入和随后的退火来隔离散热片。

26. 发明申请

US20080265321A1 Fin Field-Effect Transistors 有权
标题翻译：鳍场效应晶体管
公开(公告)号：US20080265321A1
公开(公告)日：2008-10-30
申请号：US11741602
申请日：2007-04-27
申请人： Chen-Hua Yu , Yu-Rung Hsu , Chen-Nan Yeh
发明人： Chen-Hua Yu , Yu-Rung Hsu , Chen-Nan Yeh
IPC分类号： H01L29/78
CPC分类号： H01L21/26586 , H01L29/66795 , H01L29/785 , H01L29/78684 , H01L2924/0002 , H01L2924/00
摘要： A fin field-effect transistor (finFET) with improved source/drain regions is provided. In an embodiment, the source/drain regions of the fin are removed while spacers adjacent to the fin remain. An angled implant is used to implant the source/drain regions near a gate electrode, thereby allowing for a more uniform lightly doped drain. The fin may be re-formed by either epitaxial growth or a metallization process. In another embodiment, the spacers adjacent the fin in the source/drain regions are removed and the fin is silicided along the sides and the top of the fin. In yet another embodiment, the fin and the spacers are removed in the source/drain regions. The fins are then re-formed via an epitaxial growth process or a metallization process. Combinations of these embodiments may also be used.
摘要翻译：提供了具有改善的源极/漏极区域的鳍状场效应晶体管（finFET）。在一个实施例中，去除鳍片的源极/漏极区域，同时留下与鳍片相邻的间隔物。倾斜的注入用于在栅电极附近注入源极/漏极区，从而允许更均匀的轻掺杂漏极。鳍可以通过外延生长或金属化过程重新形成。在另一个实施例中，去除与源极/漏极区域中的鳍片相邻的间隔物，并且翅片沿翅片的侧面和顶部被硅化。在另一个实施例中，在源极/漏极区域中去除鳍片和间隔物。然后通过外延生长工艺或金属化工艺重新形成翅片。也可以使用这些实施例的组合。

27. 发明申请

US20110147810A1 METHOD OF FABRICATING STRAINED STRUCTURE IN SEMICONDUCTOR DEVICE 有权
标题翻译：在半导体器件中制造应变结构的方法
公开(公告)号：US20110147810A1
公开(公告)日：2011-06-23
申请号：US12645834
申请日：2009-12-23
申请人： Yu-Rung Hsu , Chen-Hua Yu , Chao-Cheng Chen
发明人： Yu-Rung Hsu , Chen-Hua Yu , Chao-Cheng Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/30608 , H01L21/3065 , H01L21/3083 , H01L29/165 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a portion of the substrate, and strained structures disposed at either side of the portion of the substrate and formed of a semiconductor material different from the semiconductor substrate. The portion of the substrate is T shaped having a horizontal region and a vertical region that extends from the horizontal region in a direction away from a surface of the substrate.
摘要翻译：本公开提供了一种半导体器件，其包括半导体衬底，设置在衬底的一部分上的栅极结构以及设置在衬底的该部分的任一侧的应变结构，并且由与半导体衬底不同的半导体材料形成。衬底的部分是具有水平区域的垂直区域和从远离衬底表面的方向从水平区域延伸的垂直区域。

28. 发明授权

US07910467B2 Method for treating layers of a gate stack 有权
标题翻译：处理栅极叠层的方法
公开(公告)号：US07910467B2
公开(公告)日：2011-03-22
申请号：US12355401
申请日：2009-01-16
申请人： Yu-Rung Hsu , Chen-Hua Yu , Liang-Gi Yao
发明人： Yu-Rung Hsu , Chen-Hua Yu , Liang-Gi Yao
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/336
CPC分类号： H01L21/28176 , H01L21/268 , H01L29/4908 , H01L29/517
摘要： A method for fabricating a semiconductor device with improved performance is disclosed. The method comprises providing a semiconductor substrate; forming one or more gate stacks having an interfacial layer, a high-k dielectric layer, and a gate layer over the substrate; and performing at least one treatment on the interfacial layer, wherein the treatment comprises a microwave radiation treatment, an ultraviolet radiation treatment, or a combination thereof.
摘要翻译：公开了一种制造具有改进性能的半导体器件的方法。该方法包括提供半导体衬底; 在所述衬底上形成具有界面层，高k电介质层和栅极层的一个或多个栅极堆叠; 以及对所述界面层进行至少一种处理，其中所述处理包括微波辐射处理，紫外线辐射处理或其组合。

29. 发明授权

US09935197B2 Semiconductor devices with low junction capacitances 有权
公开(公告)号：US09935197B2
公开(公告)日：2018-04-03
申请号：US13616194
申请日：2012-09-14
申请人： Cheng-Hung Chang , Yu-Rung Hsu , Chen-Hua Yu
发明人： Cheng-Hung Chang , Yu-Rung Hsu , Chen-Hua Yu
IPC分类号： H01L27/088 , H01L29/78 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/06 , H01L29/788 , H01L29/792 , H01L21/762 , H01L29/66
CPC分类号： H01L29/7833 , H01L21/76224 , H01L21/76264 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/0653 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7881 , H01L29/792
摘要： Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.

30. 发明申请

US20100213548A1 Semiconductor Devices with Low Junction Capacitances and Methods of Fabrication Thereof 有权
标题翻译：具有低结电容的半导体器件及其制造方法
公开(公告)号：US20100213548A1
公开(公告)日：2010-08-26
申请号：US12618505
申请日：2009-11-13
申请人： Cheng-Hung Chang , Yu-Rung Hsu , Chen-Hua Yu
发明人： Cheng-Hung Chang , Yu-Rung Hsu , Chen-Hua Yu
IPC分类号： H01L29/78 , H01L29/06 , H01L21/762
CPC分类号： H01L29/7833 , H01L21/76224 , H01L21/76264 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L27/1207 , H01L29/0653 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7881 , H01L29/792
摘要： Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.
摘要翻译：描述具有低结电容的半导体器件及其制造方法。在一个实施例中，形成半导体器件的方法包括在衬底中形成隔离区以形成有源区。有源区的侧壁由隔离区包围。隔离区域被凹入以暴露有源区域的侧壁的第一部分。有源区域的侧壁的第一部分被间隔物覆盖。隔离区域被蚀刻以暴露有源区域的侧壁的第二部分，第二部分设置在第一部分的下方。通过侧壁的暴露的第二部分蚀刻有源区域以形成侧向开口。横向开口用电介质上的旋转填充。

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