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21. 发明授权

US06998316B2 Method for fabricating read only memory including a first and second exposures to a photoresist layer 有权
标题翻译：一种用于制造只读存储器的方法，包括对光致抗蚀剂层的第一和第二曝光
公开(公告)号：US06998316B2
公开(公告)日：2006-02-14
申请号：US10708228
申请日：2004-02-18
申请人： Tahorng Yang , Henry Chung , Cheng-Chen Calvin Hsueh , Ching-Yu Chang
发明人： Tahorng Yang , Henry Chung , Cheng-Chen Calvin Hsueh , Ching-Yu Chang
IPC分类号： H01L21/8236 , H01L21/336 , H01L21/31 , H01L21/469
CPC分类号： H01L27/1126 , H01L27/105 , H01L27/11293 , Y10S438/949
摘要： A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit region has transistors. A precise layer having a plurality of first openings is formed in the memory cell region. The first openings are above the channel region of each memory cell in the memory cell array and the critical dimension of the first openings is identical. A mask layer having second openings and third openings is formed on the substrate. The second openings locate over a pre-coding memory cell region, and the third openings locate over the transistor gates. An ion implantation is performed to code the memory cell in the pre-coding memory cell region and to adjust the threshold voltage of the transistor, using the precise layer and the mask layer as a mask.
摘要翻译：只读存储器的制造方法提供具有存储单元区域和外围电路区域的衬底。存储单元区域具有存储单元阵列，并且外围电路区域具有晶体管。在存储单元区域中形成具有多个第一开口的精确层。第一开口在存储单元阵列中的每个存储单元的沟道区之上，并且第一开口的临界尺寸相同。在基板上形成具有第二开口和第三开口的掩模层。第二开口位于预编码存储单元区域上，并且第三开口位于晶体管栅极之上。执行离子注入以对预编码存储单元区域中的存储单元进行编码，并使用精确层和掩模层作为掩模来调节晶体管的阈值电压。

22. 发明授权

US06946400B2 Patterning method for fabricating integrated circuit 有权
标题翻译：集成电路制图方法
公开(公告)号：US06946400B2
公开(公告)日：2005-09-20
申请号：US10249143
申请日：2003-03-19
申请人： Henry Chung
发明人： Henry Chung
IPC分类号： H01L21/027 , H01L21/033 , H01L21/311 , H01L21/3213 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/0271 , H01L21/0273 , H01L21/0337 , H01L21/0338 , H01L21/31144
摘要： A patterning method for fabricating integrated circuits. The method includes forming a material layer over a substrate and then forming a photoresist layer over the material layer. The photoresist layer has a thickness small enough to relax the limitations when the photoresist layer is patterned in a photolithographic process. A shroud liner is formed over the photoresist layer such that height of the shroud liner is significantly greater than width of the shroud liner. Thereafter, the shroud liner undergoes a processing treatment to remove the sections attached to the sidewalls of the photoresist layer. Using the remaining shroud liner as an etching mask, an etching operation is carried out to pattern the material layer.
摘要翻译：一种用于制造集成电路的图案化方法。该方法包括在衬底上形成材料层，然后在材料层上形成光致抗蚀剂层。当光致抗蚀剂层在光刻工艺中被图案化时，光致抗蚀剂层的厚度足够小以缓解限制。护罩衬套形成在光致抗蚀剂层上方，使得护罩衬套的高度明显大于护罩衬套的宽度。此后，护罩衬里进行处理处理以除去附着在光致抗蚀剂层的侧壁上的部分。使用剩余的护罩衬垫作为蚀刻掩模，进行蚀刻操作以对材料层进行图案化。

23. 发明授权

US06867116B1 Fabrication method of sub-resolution pitch for integrated circuits 有权
标题翻译：集成电路子分辨率间距的制作方法
公开(公告)号：US06867116B1
公开(公告)日：2005-03-15
申请号：US10703453
申请日：2003-11-10
申请人： Henry Chung
发明人： Henry Chung
IPC分类号： H01L21/033 , H01L21/22 , H01L21/28 , H01L21/3213 , H01L21/38
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/28123 , H01L21/32139
摘要： A method of manufacturing a semiconductor device using a scanner, wherein the scanner is capable of realizing a minimum pitch, wherein the minimum pitch is the smallest possible pitch for the scanner, the method including providing a semiconductor substrate, forming a first layer over the semiconductor substrate, forming a second layer over the first layer, patterning the second layer to form a plurality of second layer patterns, patterning the first layer to form a plurality of first layer patterns, performing a tone reversal to form a reversed tone for the second layer patterns, and etching the first layer patterns using the reversed tone as a mask, wherein the etched first layer patterns have a final pitch size, and wherein the final pitch is smaller than the minimum pitch.
摘要翻译：一种使用扫描器制造半导体器件的方法，其中扫描器能够实现最小间距，其中最小间距是扫描器的最小可能间距，该方法包括提供半导体衬底，在半导体上形成第一层衬底，在第一层上形成第二层，图案化第二层以形成多个第二层图案，图案化第一层以形成多个第一层图案，执行色调反转以形成用于第二层的反转色调图案，并且使用反转色调作为掩模蚀刻第一层图案，其中蚀刻的第一层图案具有最终间距尺寸，并且其中最终间距小于最小间距。

24. 发明授权

US06642139B1 Method for forming interconnection structure in an integration circuit 有权
标题翻译：在集成电路中形成互连结构的方法
公开(公告)号：US06642139B1
公开(公告)日：2003-11-04
申请号：US10187134
申请日：2002-06-28
申请人： Henry Chung
发明人： Henry Chung
IPC分类号： H01L214763
CPC分类号： H01L21/76801 , H01L21/76807 , H01L2221/1026
摘要： A method for fabricating vias and trenches in a dual-damascene multilevel interconnection structure of an integration circuit is provided. The method uses chemical vapor deposition and flowfill dielectric technology to deposit a dielectric material at low temperature for fabricating interconnection structure in an integration circuit. It comprises the following steps: (a) forming photo-resist patterns; (b) depositing a dielectric layer at low temperature by chemical vapor deposition and flowfill dielectric technologies; (c) removing the dielectric layer by chemical-mechanical polishing to expose the photo-resist patterns; (d) removing the photo-resist patterns by chemical-mechanical polishing; and (e) stabilizing the dielectric layer by thermal curing.
摘要翻译：提供了一种用于在集成电路的双镶嵌多层互连结构中制造通孔和沟槽的方法。该方法使用化学气相沉积和流动填充电介质技术在低温下沉积介电材料，以在集成电路中制造互连结构。它包括以下步骤：（a）形成光刻胶图案; （b）通过化学气相沉积和填充介质技术在低温下沉积介电层; （c）通过化学机械抛光去除介电层以露出光致抗蚀剂图案; （d）通过化学机械抛光去除光刻胶图案; 和（e）通过热固化稳定介电层。

25. 发明授权

US06559045B2 Fabrication of integrated circuits with borderless vias 有权
公开(公告)号：US06559045B2
公开(公告)日：2003-05-06
申请号：US10170612
申请日：2002-06-12
申请人： Henry Chung
发明人： Henry Chung
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/02126 , H01L21/02348 , H01L21/02351 , H01L21/3122 , H01L21/3124 , H01L21/31604 , H01L21/76825 , H01L21/76834 , H01L21/76835 , H01L21/7688
摘要： The invention relates to the formation of structures in microelectronic devices such as integrated circuit devices by means of borderless via architectures in intermetal dielectrics. An integrated circuit structure has a substrate, a layer of a second dielectric material positioned on the substrate and spaced apart metal contacts are on the layer of the second dielectric material. The metal contacts have side walls, and a lining of a first dielectric on the side walls; a space between the linings on adjacent metal contact side walls filled with the second dielectric material, a top surface of each of the metal contacts, the linings and the spaces are at a common level. An additional layer of the second dielectric material is on some of the metal contacts, linings and filled spaces. At least one via extends through the additional layer of the second dielectric material and extends to the top surface of at least one metal contact and optionally at least one of the linings.

26. 发明授权

US06498399B2 Low dielectric-constant dielectric for etchstop in dual damascene backend of integrated circuits 有权
标题翻译：用于集成电路双镶嵌后端中蚀刻阻挡层的低介电常数电介质
公开(公告)号：US06498399B2
公开(公告)日：2002-12-24
申请号：US09391721
申请日：1999-09-08
申请人： Henry Chung , James Lin
发明人： Henry Chung , James Lin
IPC分类号： H01L23485
CPC分类号： H01L21/76835 , H01L21/76807 , H01L21/76808 , H01L21/76829
摘要： The invention provides microelectronic devices such as integrated circuit devices. Such have vias, interconnect metallization and wiring lines using dissimilar low dielectric constant intermetal dielectrics. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. A microelectronic device is formed having a substrate and a layer of a first dielectric material positioned on the substrate. A layer of a second dielectric material is positioned on the first dielectric layer and an additional layer of the first dielectric material positioned on the second dielectric material. At least one via extends through the first dielectric material layer and the second dielectric material layer, and at least one trench extends through the additional layer of the first dielectric material to the via. A lining of a barrier metal is formed on inside walls and a floor of the trench and on inside walls and a floor the via. A fill metal fills the trench and via in contact with the lining of the barrier metal.
摘要翻译：本发明提供了诸如集成电路器件的微电子器件。这样具有通孔，互连金属化和使用不同的低介电常数金属间电介质的布线。由于两种电介质的等离子体蚀刻特性明显不同，因此使用有机和无机低k电介质都有优势。一个电介质用作蚀刻其它电介质的蚀刻步骤，因此不需要额外的蚀刻阻挡层。形成具有衬底和位于衬底上的第一介电材料层的微电子器件。第二电介质材料层位于第一电介质层上，第一电介质材料的另一层位于第二电介质材料上。至少一个通孔延伸穿过第一介电材料层和第二介电材料层，并且至少一个沟槽延伸穿过第一介电材料的附加层到通孔。阻挡金属的衬里形成在内壁和沟槽的地板以及内壁和地板上的通孔上。填充金属填充与阻挡金属的衬里接触的沟槽和通孔。

27. 发明授权

US06472124B1 Self-aligned metal-insulator-metal capacitor for integrated circuits 有权
标题翻译：用于集成电路的自对准金属 - 绝缘体 - 金属电容器
公开(公告)号：US06472124B1
公开(公告)日：2002-10-29
申请号：US09710712
申请日：2000-11-10
申请人： Henry Chung
发明人： Henry Chung
IPC分类号： G03F736
CPC分类号： H01L28/60 , H01L21/3212 , H01L21/76838 , H01L28/55
摘要： A fabrication method for a self-aligned metal-insulator-metal capacitor is described. A plurality of metal interconnects is provided. A metal interconnect is etched back to form a recess in the metal interconnect using a patterned photoresist as a mask. A capacitor insulator is formed on the resulting structure, partially filling the recess in the metal interconnect and covering other metal interconnects. A top electrode metal layer is then deposited on the capacitor insulator, completely filling the recess in the metal interconnect. The top electrode metal layer that is formed above the recess of the metal interconnect is subsequently removed.
摘要翻译：描述了自对准金属 - 绝缘体 - 金属电容器的制造方法。提供多个金属互连。使用图案化的光致抗蚀剂作为掩模，将金属互连件回蚀以在金属互连中形成凹陷。在所得结构上形成电容绝缘体，部分地填充金属互连中的凹槽并覆盖其它金属互连。然后将顶部电极金属层沉积在电容器绝缘体上，完全填充金属互连中的凹槽。随后去除形成在金属互连件的凹部上方的顶部电极金属层。

28. 发明授权

US06383912B1 Fabrication method of integrated circuits with multiple low dielectric-constant intermetal dielectrics 失效
标题翻译：具有多个低介电常数的金属间电介质的集成电路的制造方法
公开(公告)号：US06383912B1
公开(公告)日：2002-05-07
申请号：US09694194
申请日：2000-10-23
申请人： Henry Chung , James Lin
发明人： Henry Chung , James Lin
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/76807 , H01L21/76813 , H01L21/76825 , H01L21/76828 , H01L21/76835 , H01L2221/1031
摘要： The invention provides process for producing microelectronic devices such as integrated circuit devices. Such have vias, interconnect metallization and wiring lines using dissimilar low dielectric constant intermetal dielectrics. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. A microelectronic device is formed having a substrate and a layer of a first dielectric material positioned on the substrate. A layer of a second dielectric material is positioned on the first dielectric layer. Either a sacrificial metal layer or and an additional layer the first dielectric material is positioned on the second dielectric material. At least one via extends through the first dielectric material layer and at least one trench extends through the additional layer of the first dielectric material and the second dielectric material layer to the via. A lining of a barrier metal is formed on inside walls and a floor of the trench and on inside walls and a floor the via. A fill metal fills the trench and via in contact with the lining of the barrier metal.
摘要翻译：本发明提供了用于制造诸如集成电路器件的微电子器件的方法。这样具有通孔，互连金属化和使用不同的低介电常数金属间电介质的布线。由于两种电介质的等离子体蚀刻特性明显不同，因此使用有机和无机低k电介质都有优势。一个电介质用作蚀刻其它电介质的蚀刻步骤，因此不需要额外的蚀刻阻挡层。形成具有衬底和位于衬底上的第一介电材料层的微电子器件。第二电介质材料层位于第一电介质层上。牺牲金属层或附加层中的第一介电材料位于第二电介质材料上。至少一个通孔延伸穿过第一介电材料层，并且至少一个沟槽延伸穿过第一介电材料的附加层和第二介电材料层延伸至通孔。阻挡金属的衬里形成在内壁和沟槽的地板以及内壁和地板上的通孔上。填充金属填充与阻挡金属的衬里接触的沟槽和通孔。

29. 外观设计

USD1007051S1 Hookah 有权
公开(公告)号：USD1007051S1
公开(公告)日：2023-12-05
申请号：US29783182
申请日：2021-05-11
申请人： Henry Chung
设计人： Henry Chung
摘要： FIG. 1 is a front view of the hookah showing my new design.
FIG. 2 is a left side view thereof, the right side being the mirror image.
FIG. 3 is a rear view thereof.
FIG. 4 is a top view thereof; and,
FIG. 5 is a bottom view thereof.
The broken lines in the drawings depict portions of the hookah that form no part of the claimed design.

30. 发明申请

US20220183353A1 Combination Hookah and Plasma Light 有权
公开(公告)号：US20220183353A1
公开(公告)日：2022-06-16
申请号：US17582498
申请日：2022-01-24
申请人： Henry Chung
发明人： Henry Chung
IPC分类号： A24F1/30 , A24F13/00 , B03C3/34 , H01T23/00
摘要： A hookah includes a negative ion emitter radiating negative ions into an area around the hookah. Smokers may exhale smoke into the area of the negative ions and the negative ions react with elements in the smoke purifying the surrounding air. An example of a negative ion emitter is a plasma light.

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