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21. 发明授权

US06444573B1 Method of making a slot via filled dual damascene structure with a middle stop layer 有权
标题翻译：通过具有中间停止层的填充双镶嵌结构制造槽的方法
公开(公告)号：US06444573B1
公开(公告)日：2002-09-03
申请号：US09788472
申请日：2001-02-21
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808 , Y10S977/888
摘要： An interconnect structure and method of forming the same in which a first inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a slot via in the first dielectric layer. The slot via is longer than the width of a subsequently formed trench. A second low k dielectric material is deposited within the slot via and over the etch stop layer, to form a second dielectric layer over the slot via and the etch stop layer. The re-filled slot via is simultaneously etched with the second dielectric layer in which a trench is formed. The entire width of the trench is over the via that is etched. The re-opened via and the trench are filled with a conductive material.
摘要翻译：一种互连结构及其形成方法，其中第一无机低k电介质材料沉积在导电层上以形成第一介电层。在第一电介质层上形成蚀刻停止层。蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成槽通孔。狭缝通孔比随后形成的沟槽的宽度长。第二低k电介质材料通过蚀刻停止层上方和上方沉积在槽内，以在槽通孔和蚀刻停止层上形成第二电介质层。再填充的槽通孔与其中形成沟槽的第二电介质层同时蚀刻。沟槽的整个宽度在被蚀刻的通孔之上。重新打开的通孔和沟槽填充有导电材料。

22. 发明授权

US06365505B1 Method of making a slot via filled dual damascene structure with middle stop layer 有权
标题翻译：通过具有中间停止层的填充双镶嵌结构制作槽的方法
公开(公告)号：US06365505B1
公开(公告)日：2002-04-02
申请号：US09780531
申请日：2001-02-21
申请人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
发明人： Fei Wang , Lynne A. Okada , Ramkumar Subramanian , Calvin T. Gabriel
IPC分类号： H01L214763
CPC分类号： H01L21/76835 , H01L21/76808
摘要： A method of forming an interconnect structure in which an inorganic low k dielectric material is deposited over a conductive layer to form a first dielectric layer. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a slot via in the first dielectric layer. The slot via is longer than the width of a subsequently formed trench. An organic low k dielectric material is deposited within the slot via and over the etch stop layer to form a second dielectric layer over the slot via and the etch stop layer. The re-filled slot via is simultaneously etched with the second dielectric layer in which a trench is formed. The entire width of the trench is directly over the via. The re-opened via and the trench are filled with a conductive material.
摘要翻译：一种形成互连结构的方法，其中无机低k电介质材料沉积在导电层上以形成第一介电层。在第一电介质层上形成蚀刻停止层。蚀刻停止层和第一介电层被蚀刻以在第一介电层中形成槽通孔。狭缝通孔比随后形成的沟槽的宽度长。有机低k电介质材料通过蚀刻停止层上方和上方沉积在槽内，以在缝隙通孔和蚀刻停止层上形成第二电介质层。再填充的槽通孔与其中形成沟槽的第二电介质层同时蚀刻。沟槽的整个宽度直接在通孔上方。重新打开的通孔和沟槽填充有导电材料。

23. 发明授权

US06492272B1 Carrier gas modification for use in plasma ashing of photoresist 失效
标题翻译：载体气体改性用于光刻胶的等离子体灰化
公开(公告)号：US06492272B1
公开(公告)日：2002-12-10
申请号：US09805975
申请日：2001-03-15
申请人： Lynne A. Okada , Fei Wang
发明人： Lynne A. Okada , Fei Wang
IPC分类号： H01L2100
CPC分类号： H01L21/31138 , G03F7/427 , H01L21/31116 , H01L21/76802
摘要： Deleterious physical sputtering of workpiece layers accompanying removal of photoresist layers from the workpiece by plasma ashing utilizing an active plasma ashing gas such as O2, N2, N2/O2, or H2/N2 gas mixtures admixed with Ar inert carrier gas/diluent, is eliminated, or at least substantially reduced, by replacing the Ar with an inert gas of greater atomic weight, such as Kr or Xe, and supplying a lower level of electrical power to the plasma reactor than when Ar is utilized.
摘要翻译：消除了伴随Ar惰性载气/稀释剂混合的活性等离子体灰化气体如O 2，N 2，N 2 / O 2或H 2 / N 2气体混合物的等离子体灰化从工件中除去光致抗蚀剂层的工件层的有害物理溅射，或至少大大减少，通过用较大原子量的惰性气体例如Kr或Xe代替Ar，并且比使用Ar时向等离子体反应器提供较低水平的电功率。

24. 发明授权

US06767827B1 Method for forming dual inlaid structures for IC interconnections 有权
标题翻译：用于形成用于IC互连的双镶嵌结构的方法
公开(公告)号：US06767827B1
公开(公告)日：2004-07-27
申请号：US10459328
申请日：2003-06-11
申请人： Lynne A. Okada , Fei Wang , James Kai
发明人： Lynne A. Okada , Fei Wang , James Kai
IPC分类号： H01L214763
CPC分类号： H01L21/76832 , H01L21/76808 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L2221/1063
摘要： A method for forming a dual inlaid interconnect structure for ICs is disclosed. The method includes forming an etch stop layer, opening a portion of the etch stop layer on an IC die, forming a first dielectric layer, a middle stop layer, a second dielectric layer and a cap layer thereover. The method further comprises patterning the cap, dielectric layers and middle stop layer a via opening down to the etch stop layer that is associated with the opening therein. A trench opening is formed down through the cap and second dielectric layer and stopping on the middle stop layer. The trench/via opening is then filled with a conductive material (e.g., metal). The method may further include forming a barrier layer within the opening of the etch stop layer. According to another aspect of the invention, a first and second etch stop layer are formed over the substrate and the second etch stop layer is patterned to define two regions, wherein a second region having the first and second etch stop layers experiences a faster etch rate than the first region. The first dielectric layer, middle stop layer, second dielectric layer and cap layer are then deposited over both regions and two via openings are formed therethrough in the regions, respectively. The first and second etch stop layers protect the underlying substrate from experiencing punchthrough during the via formation. A trench pattern is then defined in the second dielectric layer and the etch stop layers are then removed in the openings and a conductive material is formed therein.
摘要翻译：公开了一种形成用于IC的双镶嵌互连结构的方法。该方法包括形成蚀刻停止层，在IC管芯上打开蚀刻停止层的一部分，在其上形成第一介电层，中间停止层，第二介电层和盖层。该方法还包括将盖，电介质层和中间停止层的图形图案化，通孔向下通向与其中的开口相关联的蚀刻停止层。通过盖和第二介电层向下形成沟槽开口，并在中间停止层上停止。然后用导电材料（例如金属）填充沟槽/通孔开口。该方法还可以包括在蚀刻停止层的开口内形成阻挡层。根据本发明的另一方面，在衬底上形成第一和第二蚀刻停止层，并且将第二蚀刻停止层图案化以限定两个区域，其中具有第一和第二蚀刻停止层的第二区域经历更快的蚀刻速率比第一个地区。然后在两个区域上沉积第一介电层，中间阻挡层，第二介电层和盖层，并且在该区域中分别形成两个通孔。第一和第二蚀刻停止层在通孔形成期间保护下面的衬底不经历穿透。然后在第二电介质层中限定沟槽图案，然后在开口中去除蚀刻停止层，并在其中形成导电材料。

25. 发明授权

US06514860B1 Integration of organic fill for dual damascene process 有权
标题翻译：有机填料的整合用于双镶嵌工艺
公开(公告)号：US06514860B1
公开(公告)日：2003-02-04
申请号：US09892750
申请日：2001-06-28
申请人： Lynne A. Okada , Fei Wang , James K. Kai
发明人： Lynne A. Okada , Fei Wang , James K. Kai
IPC分类号： H01L2144
CPC分类号： H01L21/76808
摘要： A method of manufacturing a semiconductor device includes forming a second barrier layer over a first level, forming a first dielectric layer over the second barrier layer, forming a second dielectric layer over the first dielectric layer, etching the first and second dielectric layers to form an opening through the first dielectric layer and the second dielectric layer, depositing an organic fill material in the opening and removing a portion of the organic fill material before etching the second dielectric layer to form a trench. The organic fill material can then be completely removed and the second barrier layer is etched to expose the first level. The trench and a via are then filled with a conductive material to form a feature.
摘要翻译：制造半导体器件的方法包括：在第一层上形成第二阻挡层，在第二阻挡层上形成第一介电层，在第一介电层上形成第二电介质层，蚀刻第一和第二电介质层，形成第通过第一电介质层和第二电介质层开口，在蚀刻第二介电层之前将有机填充材料沉积在开口中并去除一部分有机填充材料以形成沟槽。然后可以完全去除有机填充材料，并且蚀刻第二阻挡层以暴露第一层。然后用导电材料填充沟槽和通孔以形成特征。

26. 发明授权

US06872663B1 Method for reworking a multi-layer photoresist following an underlayer development 失效
标题翻译：在底层显影之后再加工多层光致抗蚀剂的方法
公开(公告)号：US06872663B1
公开(公告)日：2005-03-29
申请号：US10302235
申请日：2002-11-22
申请人： Lynne A. Okada
发明人： Lynne A. Okada
IPC分类号： G03F7/09 , H01L21/027 , H01L21/302
CPC分类号： G03F7/094 , H01L21/0274
摘要： A method of processing a semiconductor device is disclosed and comprises patterning a multi-layer photoresist which comprises an imaging layer overlying an underlying layer. The patterning of the resist defines an exposed portion of an underlying process layer. The method further comprises inspecting the patterned multi-layer photoresist for defects and re-working the patterned multi-layer photoresist upon a failed inspection. The re-work process comprises depositing a protection layer over the patterned multi-layer photoresist and over the exposed portion of the underlying process layer. A portion of the protection layer and the imaging layer are then removed in a concurrent manner while leaving a remaining portion of the protection layer covering the exposed portion of the underlying process layer. A remaining portion of the protection layer and the underlying layer are then removed in a concurrent manner and such removal does not adversely impact the process layer.
摘要翻译：公开了一种处理半导体器件的方法，并且包括对包含覆盖在下层上的成像层的多层光致抗蚀剂进行图案化。抗蚀剂的图案化定义了下面的工艺层的暴露部分。该方法还包括检查图案化的多层光致抗蚀剂的缺陷并在失败的检查时重新加工图案化的多层光致抗蚀剂。重新加工过程包括在图案化的多层光致抗蚀剂上以及在底层工艺层的暴露部分上沉积保护层。然后以并行方式去除保护层和成像层的一部分，同时留下保护层的剩余部分覆盖下面的处理层的暴露部分。然后以并行方式去除保护层和下层的剩余部分，并且这种去除不会对工艺层产生不利影响。

27. 发明授权

US06756300B1 Method for forming dual damascene interconnect structure 有权
标题翻译：双镶嵌互连结构的形成方法
公开(公告)号：US06756300B1
公开(公告)日：2004-06-29
申请号：US10324259
申请日：2002-12-18
申请人： Fei Wang , Jerry Cheng , Lynne A. Okada , Minh Quoc Tran , Lu You
发明人： Fei Wang , Jerry Cheng , Lynne A. Okada , Minh Quoc Tran , Lu You
IPC分类号： H01L214763
CPC分类号： H01L21/76811 , H01L21/76813
摘要： For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material disposed over the via and trench mask materials. The via and trench mask materials exposed through the via opening of the via mask patterning material are etched away, and the via mask patterning material is etched away. A portion of the dielectric material exposed through the via opening is etched down to the underlying interconnect structure, and a portion of the dielectric material exposed through the trench opening is etched, to form the dual damascene opening.
摘要翻译：为了在介电材料内形成双镶嵌开口，在电介质材料上形成通孔掩模材料和沟槽掩模材料。通过沟槽掩模材料形成沟槽开口，并且通过布置在通孔和沟槽掩模材料上方的通孔掩模图案形成材料形成通孔开口。通过通孔掩模图形材料的通路孔露出的通孔和沟槽掩模材料被蚀刻掉，并且通孔掩模图案材料被蚀刻掉。通过通孔开口暴露的介电材料的一部分被蚀刻到下面的互连结构上，并且蚀刻通过沟槽开口露出的电介质材料的一部分，以形成双镶嵌开口。

28. 发明授权

US06713382B1 Vapor treatment for repairing damage of low-k dielectric 有权
标题翻译：用于修复低k电介质损伤的蒸气处理
公开(公告)号：US06713382B1
公开(公告)日：2004-03-30
申请号：US10059268
申请日：2002-01-31
申请人： Suzette K. Pangrle , Ecran Adem , Calvin Gabriel , Lynne A. Okada
发明人： Suzette K. Pangrle , Ecran Adem , Calvin Gabriel , Lynne A. Okada
IPC分类号： H01L214763
CPC分类号： H01L21/76802 , H01L21/76831
摘要： A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer, forming an opening having side surfaces through the dielectric layer, etching the first barrier layer, and filling the opening with metal to form a first metal feature. The process also includes the step of replacing hydroxyl terminated ions on the side surfaces. This step of replacing the hydroxyl terminated ions can occur after the opening is formed or after the first barrier layer is etched. A semiconductor device produced by the method of manufacturing is also disclosed.
摘要翻译：一种制造半导体器件的方法包括形成第一层，在第一层上形成第一势垒层，在第一阻挡层上形成电介质层，形成通过介电层的侧表面的开口，蚀刻第一阻挡层，并用金属填充开口以形成第一金属特征。该方法还包括在侧表面上置换羟基封端的离子的步骤。取代羟基封端的离子的该步骤可以在形成开口之后或在第一阻挡层被蚀刻之后发生。还公开了通过制造方法制造的半导体器件。

29. 发明授权

US06656830B1 Dual damascene with silicon carbide middle etch stop layer/ARC 有权
标题翻译：双面镶嵌碳化硅中间蚀刻停止层/ ARC
公开(公告)号：US06656830B1
公开(公告)日：2003-12-02
申请号：US09777695
申请日：2001-02-07
申请人： Ramkumar Subramanian , Dawn M. Hopper , Fei Wang , Lynne A. Okada
发明人： Ramkumar Subramanian , Dawn M. Hopper , Fei Wang , Lynne A. Okada
IPC分类号： H01L214763
CPC分类号： H01L21/76843 , H01L21/76807
摘要： The dimensional accuracy of trench formation and, hence, metal line width, in damascene processing is improved by employing a silicon carbide middle etch stop layer/ARC. Embodiments include via first-trench last dual damascene techniques employing a silicon carbide middle etch stop layer/ARC having an extinction coefficient (k) of about −0.10 to about −0.60.
摘要翻译：通过采用碳化硅中间蚀刻停止层/ ARC，提高了镶嵌加工中沟槽形成的尺寸精度以及因此的金属线宽度。实施例包括使用具有约-0.10至约-0.60的消光系数（k）的碳化硅中蚀刻停止层/ ARC的第一沟槽最后双镶嵌技术。

30. 发明授权

US06309955B1 Method for using a CVD organic barc as a hard mask during via etch 有权
标题翻译：在通孔蚀刻期间使用CVD有机棒材作为硬掩模的方法
公开(公告)号：US06309955B1
公开(公告)日：2001-10-30
申请号：US09784065
申请日：2001-02-16
申请人： Ramkumar Subramanian , Fei Wang , Todd P. Lukanc , Lynne A. Okada
发明人： Ramkumar Subramanian , Fei Wang , Todd P. Lukanc , Lynne A. Okada
IPC分类号： H01L214763
CPC分类号： H01L21/76808
摘要： A method for forming a via of a metal interconnect structure in a semiconductor device employs a CVD organic BARC between a low k dielectric material and a via photoresist mask. The CVD organic BARC is deposited over the low k dielectric film and protects the film during formation and patterning of the via photoresist mask. Furthermore, the presence of the BARC permits the photoresist mask to be thinner than that used in conventional techniques thereby improving lithography resolution.
摘要翻译：在半导体器件中形成金属互连结构的通孔的方法在低k电介质材料和通孔光致抗蚀剂掩模之间采用CVD有机BARC。 CVD有机BARC沉积在低k电介质膜上，并在通孔光致抗蚀剂掩模的形成和图案化期间保护膜。此外，BARC的存在允许光致抗蚀剂掩模比常规技术中使用的光刻胶掩模更薄，从而提高光刻分辨率。

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