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21. 发明申请

US20090282226A1 Context Switching On A Network On Chip 有权
标题翻译：上下文切换网络芯片
公开(公告)号：US20090282226A1
公开(公告)日：2009-11-12
申请号：US12118039
申请日：2008-05-09
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F9/30
CPC分类号： G06F15/7825 , H04L49/109
摘要： A network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to the network by an application messaging interconnect including an inbox and an outbox, one or more of the IP blocks including computer processors supporting a plurality of threads, the NOC also including an inbox and outbox controller configured to set pointers to the inbox and outbox, respectively, that identify valid message data for a current thread; and software running in the current thread that, upon a context switch to a new thread, is configured to: save the pointer values for the current thread, and reset the pointer values to identify valid message data for the new thread, where the inbox and outbox controller are further configured to retain the valid message data for the current thread in the boxes until context switches again to the current thread.
摘要翻译：包括IP块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过包括收件箱和发件箱的应用消息传送互连网络适配到网络，IP网络中的一个或多个块，包括支持多个线程的计算机处理器，NOC还包括分别设置指向当前线程的有效消息数据的收件箱和发送箱的指针的收件箱和发件箱控制器; 以及在当前线程中运行的软件，在上下文切换到新线程时，配置为：保存当前线程的指针值，并重置指针值以识别新线程的有效消息数据，其中收件箱和发送箱控制器被进一步配置为将当前线程的有效消息数据保留在框中，直到上下文再次切换到当前线程。

22. 发明申请

US20090135739A1 Network On Chip With Partitions 有权
标题翻译：网络片上分区
公开(公告)号：US20090135739A1
公开(公告)日：2009-05-28
申请号：US11945396
申请日：2007-11-27
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： H04L12/28
CPC分类号： G06F15/7825 , H04L49/109 , H04L49/15 , H04L49/1546 , H04L49/3036 , H04L49/45
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, with the network organized into partitions, each partition including at least one IP block, each partition assigned exclusive access to a separate physical memory address space and one or more applications executing on one or more of the partitions.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，其中每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器的IP间块通信的每个网络接口控制器，其中网络被组织成分区，每个分区包括至少一个IP块，每个分区被分配独占访问单独的物理内存地址空间和在一个或多个分区上执行的一个或多个应用程序。

23. 发明申请

US20120203971A1 Network On Chip With Caching Restrictions For Pages Of Computer Memory 失效
标题翻译：网络片上缓存限制计算机内存页面
公开(公告)号：US20120203971A1
公开(公告)日：2012-08-09
申请号：US13445005
申请日：2012-04-12
申请人： Russell D. Hoover , Eric O. Mejdrich
发明人： Russell D. Hoover , Eric O. Mejdrich
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F12/126 , G06F15/7825
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, a multiplicity of computer processors, each computer processor implementing a plurality of hardware threads of execution; and computer memory, the computer memory organized in pages and operatively coupled to one or more of the computer processors, the computer memory including a set associative cache, the cache comprising cache ways organized in sets, the cache being shared among the hardware threads of execution, each page of computer memory restricted for caching by one replacement vector of a class of replacement vectors to particular ways of the cache, each page of memory further restricted for caching by one or more bits of a replacement vector classification to particular sets of ways of the cache.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，计算机处理器的多样性，每个计算机处理器实现多个硬件执行线程; 和计算机存储器，计算机存储器以页面组织并且可操作地耦合到一个或多个计算机处理器，该计算机存储器包括集合关联高速缓存，该高速缓存包括以集合组织的高速缓存方式，高速缓存在执行的硬件线程之间共享计算机存储器的每一页被限制用于通过一类替换向量的一个替换向量到高速缓存的特定方式进行高速缓存，存储器的每一页被进一步限制用于通过替换向量分类的一个或多个位进行高速缓存到特定的一组方式缓存。

24. 发明授权

US07917703B2 Network on chip that maintains cache coherency with invalidate commands 失效
标题翻译：使用无效命令维护高速缓存一致性的片上网络
公开(公告)号：US07917703B2
公开(公告)日：2011-03-29
申请号：US11955553
申请日：2007-12-13
申请人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0837 , G06F15/7825
摘要： A network on chip (‘NOC’) comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block coupled to a router through a memory communications controller and a network interface controller, the NOC also including a port on a router of the network through which is received an invalidate command, the invalidate command including an identification of a cache line, the invalidate command representing an instruction to invalidate the cache line, the router configured to send the invalidate command to an IP block served by the router; the router further configured to send the invalidate command horizontally and vertically to neighboring routers if the port is a vertical port; and the router further configured to send the invalidate command only horizontally to neighboring routers if the port is a horizontal port.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器耦合到路由器，NOC 还包括在通过其接收到无效命令的网络的路由器上的端口，包括高速缓存行的标识的无效命令，表示使高速缓存行无效的指令的无效命令，被配置为将无效命令发送到由路由器服务的IP块; 路由器还配置为如果端口是垂直端口，则将无效命令水平和垂直地发送到相邻路由器; 并且该路由器还被配置为仅当该端口是水平端口时才将水平地发送到相邻路由器的invalidate命令。

25. 发明申请

US20090282227A1 Monitoring Software Pipeline Performance On A Network On Chip 失效
标题翻译：监控网络芯片上的软件流水线性能
公开(公告)号：US20090282227A1
公开(公告)日：2009-11-12
申请号：US12117875
申请日：2008-05-09
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F9/30
CPC分类号： G06F11/3404 , G06F15/7825
摘要： Software pipelining on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers. Embodiments of the present invention include implementing a software pipeline on the NOC, including segmenting a computer software application into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID; executing each stage of the software pipeline on a thread of execution on an IP block; monitoring software pipeline performance in real time; and reconfiguring the software pipeline, dynamically, in real time, and in dependence upon the monitored software pipeline performance.
摘要翻译：芯片上的软件流水线（NOC），NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和路由器网络接口控制器，每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器。本发明的实施例包括在NOC上实现软件管线，包括将计算机软件应用程序分阶段分段，每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块; 在IP块上执行一个执行线程的软件流水线的每个阶段; 实时监控软件流水线性能; 并且动态地，实时地重新配置软件流水线，并且依赖于监视的软件流水线性能。

26. 发明申请

US20090157976A1 Network on Chip That Maintains Cache Coherency With Invalidate Commands 失效
标题翻译：使用无效命令维护缓存一致性的片上网络
公开(公告)号：US20090157976A1
公开(公告)日：2009-06-18
申请号：US11955553
申请日：2007-12-13
申请人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
发明人： Miguel Comparan , Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Alfred T. Watson, III
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0837 , G06F15/7825
摘要： A network on chip (‘NOC’) that maintains cache coherency with invalidate commands, the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, the NOC also including a port on a router of the network through which is received an invalidate command, the invalidate command including an identification of a cache line, the invalidate command representing an instruction to invalidate the cache line, the router configured to send the invalidate command to an IP block served by the router; the router further configured to send the invalidate command horizontally and vertically to neighboring routers if the port is a vertical port; and the router further configured to send the invalidate command only horizontally to neighboring routers if the port is a horizontal port.
摘要翻译：片上网络（“NOC”）通过无效命令维持高速缓存一致性，NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器适配于路由器通信控制器和网络接口控制器，NOC还包括接收到无效命令的网络的路由器上的端口，包括高速缓存行的标识的无效命令，表示使高速缓存行无效的指令的无效命令路由器被配置为将无效命令发送到由路由器服务的IP块; 路由器还配置为如果端口是垂直端口，则将无效命令水平和垂直地发送到相邻路由器; 并且该路由器还被配置为仅当该端口是水平端口时才将水平地发送到相邻路由器的invalidate命令。

27. 发明授权

US08572324B2 Network on chip with caching restrictions for pages of computer memory 失效
标题翻译：网络芯片具有缓存限制的计算机内存页面
公开(公告)号：US08572324B2
公开(公告)日：2013-10-29
申请号：US13445005
申请日：2012-04-12
申请人： Russell D. Hoover , Eric O. Mejdrich
发明人： Russell D. Hoover , Eric O. Mejdrich
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F12/126 , G06F15/7825
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, a multiplicity of computer processors, each computer processor implementing a plurality of hardware threads of execution; and computer memory, the computer memory organized in pages and operatively coupled to one or more of the computer processors, the computer memory including a set associative cache, the cache comprising cache ways organized in sets, the cache being shared among the hardware threads of execution, each page of computer memory restricted for caching by one replacement vector of a class of replacement vectors to particular ways of the cache, each page of memory further restricted for caching by one or more bits of a replacement vector classification to particular sets of ways of the cache.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，计算机处理器的多样性，每个计算机处理器实现多个硬件执行线程; 和计算机存储器，计算机存储器以页面组织并且可操作地耦合到一个或多个计算机处理器，该计算机存储器包括集合关联高速缓存，该高速缓存包括以集合组织的高速缓存方式，高速缓存在执行的硬件线程之间共享计算机存储器的每一页被限制用于通过一类替换向量的一个替换向量来缓存高速缓存的特定方式，每一页的存储器进一步被限制用于通过替换向量分类的一个或多个比特来缓存到特定的一组方式缓存。

28. 发明授权

US08526422B2 Network on chip with partitions 有权
标题翻译：网络芯片与分区
公开(公告)号：US08526422B2
公开(公告)日：2013-09-03
申请号：US11945396
申请日：2007-11-27
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： H04L12/28
CPC分类号： G06F15/7825 , H04L49/109 , H04L49/15 , H04L49/1546 , H04L49/3036 , H04L49/45
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, with the network organized into partitions, each partition including at least one IP block, each partition assigned exclusive access to a separate physical memory address space and one or more applications executing on one or more of the partitions.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，其中每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器的IP间块通信的每个网络接口控制器，其中网络被组织成分区，每个分区包括至少一个IP块，每个分区被分配独占访问单独的物理内存地址空间和在一个或多个分区上执行的一个或多个应用程序。

29. 发明申请

US20120192202A1 Context Switching On A Network On Chip 审中-公开
标题翻译：上下文切换网络芯片
公开(公告)号：US20120192202A1
公开(公告)日：2012-07-26
申请号：US13440589
申请日：2012-04-05
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F9/46
CPC分类号： G06F15/7825 , H04L49/109
摘要： A network on chip (NOC) that includes IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to the network by an application messaging interconnect including an inbox and an outbox, one or more of the IP blocks including computer processors supporting a plurality of threads, the NOC also including an inbox and outbox controller configured to set pointers to the inbox and outbox, respectively, that identify valid message data for a current thread; and software running in the current thread that, upon a context switch to a new thread, is configured to: save the pointer values for the current thread, and reset the pointer values to identify valid message data for the new thread, where the inbox and outbox controller are further configured to retain the valid message data for the current thread in the boxes until context switches again to the current thread.
摘要翻译：包括IP块，路由器，存储器通信控制器和网络接口控制器的片上网络（NOC），每个IP块通过包括收件箱和发件箱的应用消息传送互连网络适配于网络，所述IP块中的一个或多个包括支持多个线程的计算机处理器，NOC还包括分别设置用于标识当前线程的有效消息数据的收件箱和发送箱的指针的收件箱和发送箱控制器; 以及在当前线程中运行的软件，在上下文切换到新线程时，配置为：保存当前线程的指针值，并重置指针值以识别新线程的有效消息数据，其中收件箱和发送箱控制器被进一步配置为将当前线程的有效消息数据保留在框中，直到上下文再次切换到当前线程。

30. 发明授权

US08214845B2 Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data 有权
标题翻译：通过线程保存和恢复指向包含有效消息数据的存储器阵列的指针，片上网络中的上下文切换
公开(公告)号：US08214845B2
公开(公告)日：2012-07-03
申请号：US12118039
申请日：2008-05-09
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F9/46 , G06F13/00 , G06F9/00
CPC分类号： G06F15/7825 , H04L49/109
摘要： A network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to the network by an application messaging interconnect including an inbox and an outbox, one or more of the IP blocks including computer processors supporting a plurality of threads, the NOC also including an inbox and outbox controller configured to set pointers to the inbox and outbox, respectively, that identify valid message data for a current thread; and software running in the current thread that, upon a context switch to a new thread, is configured to: save the pointer values for the current thread, and reset the pointer values to identify valid message data for the new thread, where the inbox and outbox controller are further configured to retain the valid message data for the current thread in the boxes until context switches again to the current thread.
摘要翻译：包括IP块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过包括收件箱和发件箱的应用消息传送互连网络适配到网络，IP网络中的一个或多个块，包括支持多个线程的计算机处理器，NOC还包括分别设置指向当前线程的有效消息数据的收件箱和发送箱的指针的收件箱和发件箱控制器; 以及在当前线程中运行的软件，在上下文切换到新线程时，配置为：保存当前线程的指针值，并重置指针值以识别新线程的有效消息数据，其中收件箱和发送箱控制器被进一步配置为将当前线程的有效消息数据保留在框中，直到上下文再次切换到当前线程。

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