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    • 27. 发明授权
    • Configurable data path architecture and clocking scheme
    • 可配置数据路径架构和时钟方案
    • US07535772B1
    • 2009-05-19
    • US10877932
    • 2004-06-25
    • Suresh ParameswaranThinh Tran
    • Suresh ParameswaranThinh Tran
    • G11C7/00
    • G11C7/1078G11C7/1051G11C7/106G11C7/1066G11C7/1087G11C7/1093
    • Data paths (100 and 900) can be configured to accommodate two or four burst data sequences, with a data value being input/output each half clock cycle. A data sequence can be a fixed order or user-defined order depending upon a selected option. A data input path (100) can reduce power consumption with an enable signal (dinen) timed to activate after data input lines have settled values. A data output path (900) can access output data in a parallel fashion for subsequent output according to a burst sequence. Cycle latencies for such output data can include one clock cycle latency or one and a half-clock cycles. A data output path (900) can also accommodate various clocking modes, including: single clocking with a delay locked loop (DLL) type circuit enabled, single clocking with a delay locked loop (DLL) type circuit disabled, and double clocking, with a phase difference between an input clock and output clock of up to 180°.
    • 可以将数据路径(100和900)配置为容纳两个或四个突发数据序列,其中数据值每半个时钟周期被输入/输出。 取决于所选择的选项,数据序列可以是固定顺序或用户定义的顺序。 数据输入路径(100)可以通过在数据输入线具有稳定值之后定时激活的使能信号(dinen)来降低功耗。 数据输出路径(900)可以并行地访问输出数据,以便根据突发序列进行后续输出。 这种输出数据的周期延迟可以包括一个时钟周期延迟或一个半个时钟周期。 数据输出路径(900)还可以适应各种时钟模式,包括:启用延迟锁定环路(DLL)类型电路的单一时钟,禁用延迟锁定环路(DLL)类型电路的单时钟,双时钟 输入时钟和输出时钟之间的相位差可达180°。