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21. 发明授权

US09442737B2 Restricting processing within a processor to facilitate transaction completion 有权
公开(公告)号：US09442737B2
公开(公告)日：2016-09-13
申请号：US13524833
申请日：2012-06-15
申请人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
发明人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
IPC分类号： G06F9/30 , G06F9/38 , G06F9/52 , G06F9/46
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/38 , G06F9/3857 , G06F9/466 , G06F9/467 , G06F9/52 , G06F9/524
摘要： Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.

22. 发明申请

US20130339696A1 SELECTIVELY BLOCKING BRANCH INSTRUCTION PREDICTION 有权
标题翻译：选择性阻塞分支指导预测
公开(公告)号：US20130339696A1
公开(公告)日：2013-12-19
申请号：US13524402
申请日：2012-06-15
申请人： James J. Bonanno , Ulrich Mayer , Anthony Saporito , Chung-Lung K. Shum , Timothy J. Slegel
发明人： James J. Bonanno , Ulrich Mayer , Anthony Saporito , Chung-Lung K. Shum , Timothy J. Slegel
IPC分类号： G06F9/38
CPC分类号： G06F9/38 , G06F9/30076 , G06F9/3844 , G06F9/3848
摘要： Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.
摘要翻译：实施例涉及选择性地阻止分支指令预测。一个方面包括用于执行选择性分支预测的计算机系统。系统包括存储器和处理器，并且系统被配置为执行方法。该方法包括：根据检测分支预测阻断指令，在分支预测阻塞指令之后检测指令流中的分支预测分块指令并阻止预分支数量的分支指令的分支预测。

23. 发明授权

US07111196B2 System and method for providing processor recovery in a multi-core system 有权
标题翻译：在多核系统中提供处理器恢复的系统和方法
公开(公告)号：US07111196B2
公开(公告)日：2006-09-19
申请号：US10435563
申请日：2003-05-12
申请人： Douglas G. Balazich , Michael Billeci , Anthony Saporito , Timothy J. Slegel
发明人： Douglas G. Balazich , Michael Billeci , Anthony Saporito , Timothy J. Slegel
IPC分类号： G06F11/00
CPC分类号： G06F11/2028 , G06F11/2038 , G06F11/2051
摘要： An embodiment of the invention is a multiprocessor system for detecting and recovering from errors. The multiprocessor system includes a first processor and a second processor. The first processor detects an error and initiates a recovery process. The first processor and said second processor synchronize at least one recovery action during the recovery process.
摘要翻译：本发明的实施例是用于检测和从错误中恢复的多处理器系统。多处理器系统包括第一处理器和第二处理器。第一个处理器检测到错误并启动恢复过程。第一处理器和所述第二处理器在恢复过程期间同步至少一个恢复动作。

24. 发明授权

US09891922B2 Selectively blocking branch prediction for a predetermined number of instructions 有权
公开(公告)号：US09891922B2
公开(公告)日：2018-02-13
申请号：US13524402
申请日：2012-06-15
申请人： James J. Bonanno , Ulrich Mayer , Anthony Saporito , Chung-Lung K. Shum , Timothy J. Slegel
发明人： James J. Bonanno , Ulrich Mayer , Anthony Saporito , Chung-Lung K. Shum , Timothy J. Slegel
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/38 , G06F9/30076 , G06F9/3844 , G06F9/3848
摘要： Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.

25. 发明授权

US07603543B2 Method, apparatus and program product for enhancing performance of an in-order processor with long stalls 失效
标题翻译：用于提高具有长档位的处理器性能的方法，装置和程序产品
公开(公告)号：US07603543B2
公开(公告)日：2009-10-13
申请号：US11055862
申请日：2005-02-11
申请人： Miles Robert Dooley , Scott Bruce Frommer , Hung Qui Le , Sheldon B. Levenstein , Anthony Saporito
发明人： Miles Robert Dooley , Scott Bruce Frommer , Hung Qui Le , Sheldon B. Levenstein , Anthony Saporito
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention comprises a data structure including information used by the processor. The data structure includes a group of bits to keep track of which instructions preceded a rejected instruction and therefore will be allowed to complete and which instructions follow the rejected instruction. The group of bits comprises a bit indicating whether a reject was a fast or slow reject; and a bit for each cycle that represents a state of an instruction passing through a pipeline. The processor speculatively continues to execute a set bit's corresponding instruction during stalled periods in order to generate addresses that will be needed when the stall period ends and normal dispatch resumes.
摘要翻译：一种方法，系统和计算机程序产品，用于增强具有长档位的按顺序微处理器的性能。特别地，本发明的机构提供了一种用于在处理器内存储数据的数据结构。本发明的机构包括包括由处理器使用的信息的数据结构。数据结构包括一组比特，用于跟踪被拒绝指令之前的哪些指令，因此将被允许完成，以及哪些指令遵循被拒绝的指令。该比特组包括指示拒绝是否是快速或慢速拒绝的位; 以及表示通过管道的指令的状态的每个周期的一点。处理器推测地在停滞时段期间继续执行设置位的相应指令，以便产生在停滞期结束并且恢复正常调度时将需要的地址。

26. 发明申请

US20060184772A1 Lookahead mode sequencer 失效
标题翻译：前瞻模式音序器
公开(公告)号：US20060184772A1
公开(公告)日：2006-08-17
申请号：US11055862
申请日：2005-02-11
申请人： Miles Dooley , Scott Frommer , Hung Le , Sheldon Levenstein , Anthony Saporito
发明人： Miles Dooley , Scott Frommer , Hung Le , Sheldon Levenstein , Anthony Saporito
IPC分类号： G06F9/30
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention comprises a data structure including information used by the processor. The data structure includes a group of bits to keep track of which instructions preceded a rejected instruction and therefore will be allowed to complete and which instructions follow the rejected instruction. The group of bits comprises a bit indicating whether a reject was a fast or slow reject; and a bit for each cycle that represents a state of an instruction passing through a pipeline. The processor speculatively continues to execute a set bit's corresponding instruction during stalled periods in order to generate addresses that will be needed when the stall period ends and normal dispatch resumes.
摘要翻译：一种方法，系统和计算机程序产品，用于增强具有长档位的按顺序微处理器的性能。特别地，本发明的机构提供了一种用于在处理器内存储数据的数据结构。本发明的机构包括包括由处理器使用的信息的数据结构。数据结构包括一组比特，用于跟踪被拒绝指令之前的哪些指令，因此将被允许完成，以及哪些指令遵循被拒绝的指令。该比特组包括指示拒绝是否是快速或慢速拒绝的位; 以及表示通过管道的指令的状态的每个周期的一点。处理器推测地在停滞时段期间继续执行设置位的相应指令，以便产生在停滞期结束并且恢复正常调度时将需要的地址。

27. 发明授权

US07831775B2 System and method for tracking changes in L1 data cache directory 有权
标题翻译：用于跟踪L1数据缓存目录中的更改的系统和方法
公开(公告)号：US07831775B2
公开(公告)日：2010-11-09
申请号：US12131432
申请日：2008-06-02
申请人： Sheldon B. Levenstein , Anthony Saporito
发明人： Sheldon B. Levenstein , Anthony Saporito
IPC分类号： G06F12/00
CPC分类号： G06F12/0855
摘要： Method, system and computer program product for tracking changes in an L1 data cache directory. A method for tracking changes in an L1 data cache directory determines if data to be written to the L1 data cache is to be written to an address to be changed from an old address to a new address. If it is determined that the data to be written is to be written to an address to be changed, a determination is made if the data to be written is associated with the old address or the new address. If it is determined that the data is to be written to the new address, the data is allowed to be written to the new address following a prescribed delay after the address to be changed is changed. The method is preferably implemented in a system that provides a Store Queue (STQU) design that includes a Content Addressable Memory (CAM)-based store address tracking mechanism that includes early and late write CAM ports. The method eliminates time windows and the need for an extra copy of the L1 data cache directory.
摘要翻译：方法，系统和计算机程序产品，用于跟踪L1数据缓存目录中的更改。用于跟踪L1数据高速缓存目录中的变化的方法确定要写入L1数据高速缓存的数据是否被写入要从旧地址改变到新地址的地址。如果确定要写入的数据要写入要改变的地址，则确定要写入的数据是否与旧地址或新地址相关联。如果确定要将数据写入新地址，则在要更改的地址改变之后，允许将数据写入到遵循规定延迟的新地址。该方法优选地在提供包括基于内容寻址存储器（CAM）的存储地址跟踪机制的存储队列（STQU）设计的系统中实现，该机制包括早期和晚期写入CAM端口。该方法消除了时间窗口，并需要额外的L1数据高速缓存目录副本。

28. 发明授权

US07805634B2 Error accumulation register, error accumulation method, and error accumulation system 失效
标题翻译：误差累积寄存器，误差累积法和误差累积系统
公开(公告)号：US07805634B2
公开(公告)日：2010-09-28
申请号：US11522132
申请日：2006-09-16
申请人： Douglas G. Balazich , Michael Billeci , Anthony Saporito , Timothy J. Slegel
发明人： Douglas G. Balazich , Michael Billeci , Anthony Saporito , Timothy J. Slegel
IPC分类号： G06F11/00
CPC分类号： G06F11/0772 , G06F11/0724 , G06F11/1407
摘要： In operating a dual core processor, a register file collects a history of the error state information for each core. The core error state data can be analyzed to understand the recovery sequence of events. The recorded error sequence over time presents a detailed history of the recovery sequence which is useful to understand complex error scenarios.
摘要翻译：在操作双核处理器时，寄存器文件收集每个核心的错误状态信息的历史记录。可以分析核心错误状态数据，以了解事件的恢复顺序。随着时间的推移，记录的错误序列提供了恢复序列的详细历史，这对于了解复杂的错误情况是有用的。

29. 发明授权

US07752354B2 Auxiliary mechanism to manage instruction restart and restart coming in a lookahead processor 有权
标题翻译：辅助机制，用于管理指令重新启动和重新启动进入前瞻处理器
公开(公告)号：US07752354B2
公开(公告)日：2010-07-06
申请号：US11055844
申请日：2005-02-11
申请人： Miles Robert Dooley , Joaquin Hinojosa , Bruce Joseph Ronchetti , Anthony Saporito
发明人： Miles Robert Dooley , Joaquin Hinojosa , Bruce Joseph Ronchetti , Anthony Saporito
IPC分类号： G06F3/00 , G06F12/00
CPC分类号： G06F9/3861 , G06F9/3842 , G06F11/141
摘要： A management system that controls a restart interface in a data processing system. The management system switches control of the interface from a distributed network managed by the caches to the management system. The management system is capable of detecting errors and seizing control of the interface in order to remedy any errors that occur within the interface.
摘要翻译：控制数据处理系统中的重启界面的管理系统。管理系统将接口控制从高速缓存管理的分布式网络切换到管理系统。管理系统能够检测错误并占用接口的控制，以补救接口内发生的任何错误。

30. 发明申请

US20080209177A1 Mechanism in a Multi-Threaded Microprocessor to Maintain Best Case Demand Instruction Redispatch 有权
标题翻译：多线程微处理器中维护最佳案例需求指令重新分配的机制
公开(公告)号：US20080209177A1
公开(公告)日：2008-08-28
申请号：US12113561
申请日：2008-05-01
申请人： Scott Bruce Frommer , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
发明人： Scott Bruce Frommer , Sheldon B. Levenstein , Bruce Joseph Ronchetti , Anthony Saporito
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F12/0897
摘要： A method and system for maintaining a best-case demand redispatch of an instruction to allow for maximizing the time a rejected thread may execute in lookahead execution mode, while maintaining the smallest L1 cache miss penalty supported by the memory subsystem. In response to a demand miss, a load/store unit sends a fetch request to the next level cache. The cache line of the demand miss is examined to identify the critical sector. Once the critical sector is identified, a best-case data return time is determined based on the fastest time the next level cache is able to return the critical sector of the cache line. The load/store unit then sends a speculative warning to the dispatch unit to coincide with the best-case data return, wherein the speculative warning prepares the dispatch unit to resend the instruction for execution as soon as data is available to the processor core.
摘要翻译：一种方法和系统，用于维持指令的最佳情况需求重新分配，以允许最大化被拒绝的线程可以在前瞻执行模式中执行的时间，同时保持由存储器子系统支持的最小的L1高速缓存未命中。响应于需求未命中，加载/存储单元向下一级高速缓存发送提取请求。检查需求缺失的高速缓存行以确定关键部门。一旦确定了关键扇区，则最佳情况下的数据返回时间是基于下一级高速缓存能够返回高速缓存线的关键扇区的最快时间来确定的。加载/存储单元然后向调度单元发送与最佳情况数据返回一致的推测警告，其中，一旦数据可用于处理器核心，推测警告就准备调度单元重新发送执行指令。

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