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21. 发明授权

US07855111B2 Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substrates 有权
标题翻译：混合取向技术（HOT）直接硅键合（DSB）衬底的边界区域缺陷减少
公开(公告)号：US07855111B2
公开(公告)日：2010-12-21
申请号：US12538048
申请日：2009-08-07
申请人： Haowen Bu , Shaofeng Yu , Angelo Pinto , Ajith Varghese
发明人： Haowen Bu , Shaofeng Yu , Angelo Pinto , Ajith Varghese
IPC分类号： H01L21/8238 , H01L27/118
CPC分类号： H01L21/26506 , H01L21/187 , H01L21/324 , H01L21/76264 , H01L21/823807 , H01L21/823892 , H01L29/045 , H01L29/665
摘要： Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.
摘要翻译：用于CMOS IC的混合取向技术（HOT）衬底包括用于NMOS的（100）取向硅区域和用于优化各个MOS晶体管中的载流子迁移率的用于PMOS的（110）区域。（100）和（110）区域之间的边界区域必须足够窄以支持高栅极密度和SRAM单元。本发明提供一种形成含有两个不同硅晶格取向的区域的HOT衬底的方法，边界形貌小于40纳米宽。从（100）衬底晶片和（110）DBS层的直接硅键合（DSB）晶片开始，DSB层中的NMOS区域被双注入物非晶化，并通过固相外延（100）取向（100）取向重结晶 SPE）。退火期间的晶体缺陷通过晶片顶表面上的低温氧化物层来防止。还公开了用本发明方法形成的集成电路。

22. 发明授权

US07642610B2 Transistor gate electrode having conductor material layer 有权
标题翻译：具有导体材料层的晶体管栅电极
公开(公告)号：US07642610B2
公开(公告)日：2010-01-05
申请号：US11715703
申请日：2007-03-08
申请人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
发明人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
IPC分类号： H01L21/00
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
摘要翻译：本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

23. 发明申请

US20090315076A1 TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER 有权
标题翻译：具有导体材料层的晶体管栅极电极
公开(公告)号：US20090315076A1
公开(公告)日：2009-12-24
申请号：US12553033
申请日：2009-09-02
申请人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
发明人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian S. Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
摘要翻译：本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

24. 发明授权

US07416949B1 Fabrication of transistors with a fully silicided gate electrode and channel strain 有权
标题翻译：具有完全硅化的栅电极和通道应变的晶体管的制造
公开(公告)号：US07416949B1
公开(公告)日：2008-08-26
申请号：US11674902
申请日：2007-02-14
申请人： Michael Francis Pas , Shaofeng Yu
发明人： Michael Francis Pas , Shaofeng Yu
IPC分类号： H01L21/8234 , H01L21/3205
CPC分类号： H01L21/823814 , H01L21/28097 , H01L21/823807 , H01L21/823835 , H01L29/165 , H01L29/66545 , H01L29/66636 , H01L29/7848
摘要： Manufacturing a semiconductor device by forming first and second gates including patterning a silicon-containing layer on a substrate. Etched simultaneously the patterned silicon-containing layer of the first gate, and first substrate portions adjacent to the first gate to form a first gate electrode and source and drain openings. Forming SiGe simultaneously in first gate electrode source and drain openings. Second gate and second substrate portions are masked. SiGe is removed from an upper surface of the first gate to form a second opening therein. A metal deposited on the first and second gates forms a metal layer thereon. Annealing first and second gates to form FUSI first and second gate electrodes. A metal amount at an interface of the FUSI gate electrode layer and an underlying gate dielectric layer is greater than at a second interface of the second FUSI gate electrode layer and an underlying second gate dielectric layer.
摘要翻译：通过形成第一和第二栅极制造半导体器件，包括在衬底上图案化含硅层。同时蚀刻第一栅极的图案化含硅层，以及与第一栅极相邻的第一衬底部分，以形成第一栅极电极和源极和漏极开口。在第一栅极电极源极和漏极开口中同时形成SiGe。第二栅极和第二衬底部分被掩蔽。 SiGe从第一浇口的上表面移除以在其中形成第二开口。沉积在第一和第二栅极上的金属在其上形成金属层。退火第一和第二浇口形成FUSI第一和第二栅电极。在FUSI栅极电极层和底层栅极电介质层的界面处的金属量大于第二FUSI栅极电极层和下面的第二栅极电介质层的第二界面处的金属量。

25. 发明授权

US07341933B2 Method for manufacturing a silicided gate electrode using a buffer layer 有权
标题翻译：使用缓冲层制造硅化栅电极的方法
公开(公告)号：US07341933B2
公开(公告)日：2008-03-11
申请号：US11007569
申请日：2004-12-08
申请人： Shaofeng Yu , Haowen Bu , Jiong-Ping Lu , Lindsey Hall
发明人： Shaofeng Yu , Haowen Bu , Jiong-Ping Lu , Lindsey Hall
IPC分类号： H01L21/3205
CPC分类号： H01L29/66545 , H01L29/51 , H01L29/66507 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes providing a capped polysilicon gate electrode (290) over a substrate (210), the capped polysilicon gate electrode (290) including a buffer layer (260) located between a polysilicon gate electrode layer (250) and a protective layer (270). The method further includes forming source/drain regions (710) in the substrate (210) proximate the capped polysilicon gate electrode (290), removing the protective layer (270) and the buffer layer (260), and siliciding the polysilicon gate electrode layer (250) to form a silicided gate electrode (1110).
摘要翻译：本发明提供一种制造半导体器件的方法和集成电路的制造方法。制造半导体器件的方法以及其他步骤包括在衬底（210）上提供封盖的多晶硅栅电极（290），封装的多晶硅栅电极（290）包括位于多晶硅栅电极层（250）和保护层（270）。该方法还包括在靠近封盖的多晶硅栅极（290）的基板（210）中形成源/漏区（710），去除保护层（270）和缓冲层（260），并且将多晶硅栅电极层（250），以形成硅化物栅电极（1110）。

26. 发明申请

US20070170464A1 Transistor gate electrode having conductor material layer 有权
标题翻译：具有导体材料层的晶体管栅电极
公开(公告)号：US20070170464A1
公开(公告)日：2007-07-26
申请号：US11715703
申请日：2007-03-08
申请人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
发明人： Anand Murthy , Boyan Boyanov , Suman Datta , Brian Doyle , Been-Yih Jin , Shaofeng Yu , Robert Chau
IPC分类号： H01L31/00
CPC分类号： H01L29/1054 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L21/823857 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.
摘要翻译：本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

27. 发明申请

US20070042535A1 INTEGRATED CIRCUIT CONTAINING POLYSILICON GATE TRANSISTORS AND FULLY SILICIDIZED METAL GATE TRANSISTORS 有权
标题翻译：包含多晶硅栅极晶体管和完全硅化金属栅极晶体管的集成电路
公开(公告)号：US20070042535A1
公开(公告)日：2007-02-22
申请号：US11553839
申请日：2006-10-27
申请人： Shaofeng Yu , Benjamin McKee
发明人： Shaofeng Yu , Benjamin McKee
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L21/28518 , H01L21/28052 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L21/823878 , H01L29/4933 , H01L29/4975 , H01L29/665 , H01L29/66545
摘要： A method for manufacturing an integrated circuit 10 having transistors 20, 30 of two threshold voltages where protected transistor stacks 270 have a gate protection layer 220 that are formed with the use of a single additional mask step. Also, an integrated circuit 10 having at least one polysilicon gate transistor 20 and at least one FUSI metal gate transistor 30.
摘要翻译：一种用于制造具有两个阈值电压的晶体管20,30的集成电路10的方法，其中受保护的晶体管堆叠270具有使用单个附加掩模步骤形成的栅极保护层220。而且，具有至少一个多晶硅栅极晶体管20和至少一个FUSI金属栅极晶体管30的集成电路10。

28. 发明申请

US20050215037A1 Method for manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same 有权
标题翻译：用于制造具有硅化物栅电极的半导体器件的方法和包括其的集成电路的制造方法
公开(公告)号：US20050215037A1
公开(公告)日：2005-09-29
申请号：US10810759
申请日：2004-03-26
申请人： Jiong-Ping Lu , Haowen Bu , Shaofeng Yu , Ping Jiang
发明人： Jiong-Ping Lu , Haowen Bu , Shaofeng Yu , Ping Jiang
IPC分类号： H01L21/28 , H01L21/336 , H01L21/44 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66507 , H01L21/28097 , H01L29/4975 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device (100), among other possible steps, includes forming a polysilicon gate electrode over a substrate (110) and forming source/drain regions (170) in the substrate (110) proximate the polysilicon gate electrode. The method further includes forming a blocking layer (180) over the source/drain regions (170), the blocking layer (180) comprising a metal silicide, and siliciding the polysilicon gate electrode to form a silicided gate electrode (150).
摘要翻译：本发明提供一种制造半导体器件的方法及其制造方法，该集成电路包括该半导体器件。除了其他可能的步骤之外，用于制造半导体器件（100）的方法包括在衬底（110）上形成多晶硅栅电极，并在靠近多晶硅栅电极的衬底（110）中形成源/漏区（170）。该方法还包括在源极/漏极区域（170）上形成阻挡层（180），阻挡层（180）包括金属硅化物，并硅化多晶硅栅电极以形成硅化物栅电极（150）。

29. 发明授权

US08928047B2 MOSFET with source side only stress 有权
标题翻译： MOSFET源极只有应力
公开(公告)号：US08928047B2
公开(公告)日：2015-01-06
申请号：US13288170
申请日：2011-11-03
申请人： Samuel Zafar Nawaz , Shaofeng Yu , Jeffrey E. Brighton , Song Zhao
发明人： Samuel Zafar Nawaz , Shaofeng Yu , Jeffrey E. Brighton , Song Zhao
IPC分类号： H01L29/772 , H01L21/336 , H01L21/20 , H01L29/78 , H01L29/165 , H01L29/66
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66636 , H01L29/66659 , H01L29/7835
摘要： An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.
摘要翻译：集成电路仅包含源极侧的应力增强区域的晶体管。在DeMOS晶体管中，仅在源极上形成应力增强区域并且在漏极延伸中不形成应力增强区域增加了漏极延伸区域的电阻，从而能够形成减小面积的DeMOS晶体管。在MOS晶体管中，通过在源极侧形成应力增强区域，消除来自漏极侧的应力增强区域，降低晶体管泄漏，提高CHC可靠性。

30. 发明授权

US08603875B2 CMOS process to improve SRAM yield 有权
公开(公告)号：US08603875B2
公开(公告)日：2013-12-10
申请号：US13284519
申请日：2011-10-28
申请人： Shaofeng Yu , Russell Carlton McMullan , Wah Kit Loh
发明人： Shaofeng Yu , Russell Carlton McMullan , Wah Kit Loh
IPC分类号： H01L21/8238
CPC分类号： H01L27/1104 , H01L21/823814 , H01L21/823864 , H01L21/823871 , H01L27/0922 , H01L29/0847
摘要： An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.

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