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21. 发明授权

US08659601B1 Program sequencer for generating indeterminant length shader programs for a graphics processor 有权
标题翻译：用于为图形处理器生成不确定长度着色器程序的程序定序器
公开(公告)号：US08659601B1
公开(公告)日：2014-02-25
申请号：US11893404
申请日：2007-08-15
申请人： Justin Michael Mahan , Edward A. Hutchins , Ewa M. Kubalska , James T. Battle
发明人： Justin Michael Mahan , Edward A. Hutchins , Ewa M. Kubalska , James T. Battle
IPC分类号： G06T15/00 , G06T15/50 , G06T1/00 , G06T1/60
CPC分类号： G06T15/005 , G06F9/5083 , G06T1/20
摘要： A method for loading and executing an indeterminate length shader program. The method includes accessing a first portion of a shader program in graphics memory of a GPU and loading instructions from the first portion into a plurality of stages of the GPU to configure the GPU for program execution. A group of pixels is then processed in accordance with the instructions from the first portion. A second portion of the shader program is accessed in graphics memory of the GPU and instructions from the second portion are loaded into the plurality of stages of the GPU to configure the GPU for program execution. The group of pixels are then processed in accordance with the instructions from the second portion.
摘要翻译：一种用于加载和执行不确定长度着色器程序的方法。该方法包括访问GPU的图形存储器中的着色器程序的第一部分，并且将指令从第一部分加载到GPU的多个阶段以配置GPU用于程序执行。然后根据来自第一部分的指令对一组像素进行处理。在GPU的图形存储器中访问着色器程序的第二部分，并且来自第二部分的指令被加载到GPU的多个级中以配置GPU用于程序执行。然后根据来自第二部分的指令对像素组进行处理。

22. 发明授权

US06704026B2 Graphics fragment merging for improving pixel write bandwidth 有权
标题翻译：图形片段合并，以提高像素写入带宽
公开(公告)号：US06704026B2
公开(公告)日：2004-03-09
申请号：US09861185
申请日：2001-05-18
申请人： Steven M. Kurihara , Ewa M. Kubalska
发明人： Steven M. Kurihara , Ewa M. Kubalska
IPC分类号： G09G1140
CPC分类号： G06T15/005 , G06T1/60 , G06T11/40 , G09G5/14 , G09G5/363 , G09G5/391 , G09G5/393 , G09G2340/0407 , G09G2360/02 , G09G2360/12 , G09G2360/122
摘要： A merge unit for the merging of tiles or arrays of pixels or samples, and suitable for use in a high performance graphics system is described. The unit may improve the utilization of memory bandwidth by combining non-intersecting tiles of pixels, and hence potentially reducing the number of storage operations to the memory.
摘要翻译：描述了用于合并瓷砖或像素或样品阵列并且适合用于高性能图形系统的合并单元。该单元可以通过组合像素的非相交瓦片来改善存储器带宽的利用率，并因此潜在地减少对存储器的存储操作的数量。

23. 发明授权

US06895458B2 Opcode to turn around a bi-directional bus 有权
标题翻译：操作代码转向双向总线
公开(公告)号：US06895458B2
公开(公告)日：2005-05-17
申请号：US10090491
申请日：2002-03-04
申请人： Ewa M. Kubalska , Lisa Grenier , Yan Yan Tang , Elena M. Ing
发明人： Ewa M. Kubalska , Lisa Grenier , Yan Yan Tang , Elena M. Ing
IPC分类号： G06F13/36 , G06T15/00 , G09G5/36 , G06F13/00
CPC分类号： G09G5/363 , G06F13/36 , G06T15/005
摘要： A system for managing the control of a bi-directional data bus between a master unit and a slave unit. The master couples to the slave through a request opcode bus, a reply opcode bus and the data bus. If the master is in a bus driving state (with respect to the data bus) and receives a read request, the master relinquishes bus control and sends a read request through the request opcode bus. The slave unit assumes bus control and sends the requested data through the data bus. If the master is in a bus sensing state and receives a write request, the master sends a last read opcode to the slave via the request opcode bus, and waits for the slave to return a special token through the reply opcode bus. Upon receiving the special token the master unit assumes bus control and performs the write transaction.
摘要翻译：一种用于管理主单元和从单元之间的双向数据总线的控制的系统。主机通过请求操作码总线，应答操作码总线和数据总线耦合到从机。如果主机处于总线驱动状态（相对于数据总线）并接收到读取请求，则主机放弃总线控制并通过请求操作码总线发送读取请求。从单元假设总线控制，并通过数据总线发送所请求的数据。如果主机处于总线感测状态并接收写请求，则主机通过请求操作码总线向从机发送最后一个读操作码，并等待从机通过应答操作码总线返回特殊令牌。在接收到特殊令牌时，主单元承担总线控制并执行写入事务。

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