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21. 发明授权

US07412431B2 Method for managing multi-field classification rules relating to ingress 失效
标题翻译：管理与入口有关的多领域分类规则的方法
公开(公告)号：US07412431B2
公开(公告)日：2008-08-12
申请号：US10832958
申请日：2004-04-27
申请人： Everett A. Corl, Jr. , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Ravinder K. Sabhikhi
发明人： Everett A. Corl, Jr. , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Ravinder K. Sabhikhi
IPC分类号： G06F17/00 , G06N5/02
CPC分类号： G06N99/005
摘要： The present invention relates to a method for managing a plurality of multi-field classification rules. The method includes providing a first table that includes a plurality of entries corresponding to a plurality of rules relating to an ingress context and providing a second table that includes a plurality of entries corresponding to a plurality of rules relating to an egress context. The method also includes utilizing the first table and the second table to identify any rules relating to the ingress context and any rules relating to the egress context that match a search key.
摘要翻译：本发明涉及一种用于管理多个多场分类规则的方法。该方法包括提供第一表格，该第一表格包括对应于与入口上下文有关的多个规则的多个条目，并提供第二表格，该第二表格包括对应于与出口上下文有关的多个规则的多个条目。该方法还包括利用第一表和第二表来识别与入口上下文有关的任何规则以及与搜索关键字匹配的出口上下文相关的任何规则。

22. 发明申请

US20080162525A1 SYSTEM FOR DEFINING DATA MAPPINGS BETWEEN DATA STRUCTURES 失效
标题翻译：用于定义数据结构之间数据映射的系统
公开(公告)号：US20080162525A1
公开(公告)日：2008-07-03
申请号：US12048667
申请日：2008-03-14
申请人： Everett A. CORL , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Ravinder K. Sabhikhi
发明人： Everett A. CORL , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Ravinder K. Sabhikhi
IPC分类号： G06F17/30
CPC分类号： H03M7/30 , Y10S707/99942
摘要： Method for compressing search tree structures used in rule classification is provided. The method includes classifying packets based on filter rules, compressing a tree structure comprising multiple levels of single bit test nodes and leaf nodes, storing the compressed tree structure in a first memory structure of a storage such that the multiple levels of single bit test nodes and leaf nodes can be accessed from the first memory structure through a single memory access of the storage, collecting single bit test nodes of the tree structure that are in a lowest level of the tree structure, storing only the collected single bit test nodes within a second memory structure of the storage that is contiguous to the first memory structure, collecting leaf nodes of the tree structure, and storing only the collected leaf nodes within a third memory structure of the storage that is contiguous to second memory structure.
摘要翻译：提供了规则分类中使用的搜索树结构的压缩方法。该方法包括基于过滤器规则对分组进行分类，压缩包括多个单位测试节点和叶节点的树结构，将压缩的树结构存储在存储器的第一存储器结构中，使得多个单位测试节点和可以通过存储器的单个存储器访问从第一存储器结构访问叶节点，收集处于树结构的最低级别的树结构的单位测试节点，仅在第二存储器结构中存储所收集的单个位测试节点与第一存储器结构相邻的存储器的存储器结构，收集树结构的叶节点，以及仅存储所收集的叶节点在与第二存储器结构相邻的存储器的第三存储器结构内。

23. 发明授权

US07149749B2 Method of inserting and deleting leaves in tree table structures 失效
标题翻译：在树表结构中插入和删除叶子的方法
公开(公告)号：US07149749B2
公开(公告)日：2006-12-12
申请号：US10453245
申请日：2003-06-03
申请人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall , Sonia K. Rovner
发明人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall , Sonia K. Rovner
IPC分类号： G06F17/30
CPC分类号： G06F17/30625 , Y10S707/99936 , Y10S707/99942 , Y10S707/99943
摘要： A technique is provided to either insert or delete a leaf in a Patricia tree having a direct table and a plurality of PSCB's which decode portions of the pattern of a leaf in the tree without shutting down the functioning of the tree. A leaf having a pattern is identified as either a leaf to be inserted or deleted. Using the pattern, the tree is walked once to identify the location of the leaf to be deleted or the location where the leaf is to be inserted. If it is a delete operation, the leaf to be deleted is identified and deleted, and any relevant PSCB modified, if necessary. If it is an insert operation, the tree is walked a second time to insert the leaf and reform or create any PSCB in the chain that needs to be reformed or created. The technique also is applicable to inserting or deleting a prefix of a prefix.
摘要翻译：提供了一种技术来插入或删除具有直接表的Patricia树中的叶子，以及多个PSCB，其解码树中的叶子的图案的部分，而不关闭树的功能。具有图案的叶被识别为要插入或删除的叶。使用图案，树一次走一次，以确定要删除的叶的位置或叶被插入的位置。如果是删除操作，则要删除的叶被识别和删除，并且必要时修改任何相关的PSCB。如果是插入操作，则树第二次移动以插入叶，并在需要重新创建或创建的链中重新构建或创建任何PSCB。该技术也适用于插入或删除前缀的前缀。

24. 发明授权

US06963868B2 Multi-bit Patricia trees 失效
标题翻译：多比特Patricia树
公开(公告)号：US06963868B2
公开(公告)日：2005-11-08
申请号：US10448528
申请日：2003-05-30
申请人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall
发明人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： H04L45/00 , H04L45/56 , H04L45/7457 , Y10S707/99933
摘要： A tree structure and method to organize routing information for processing messages within a network, each message being associated with a search key of “n” bits. The processing determines where to send the message next. The structure has a direct table (DT) of 2x entries for decoding the first “x” bits of the search key, and one or more pattern search control blocks (PSCB's), each having 2m entries for decoding subsequent groups of “m” bits. Each PSCB entry and DT entry includes a pointer to data associated with a specific route, if at this point a specific routing table entry is a potential match to the search key or a pointer to a subsequent PSCB if the end of a search trail is not identified. Each PSCB entry DT entry also indicates that the search has been resolved to the end of the search trail.
摘要翻译：一种用于组织用于处理网络内的消息的路由信息的树结构和方法，每个消息与“n”比特的搜索关键字相关联。该处理确定接下来发送消息的位置。该结构具有用于对搜索关键字的第一个“x”比特进行解码的2个“<”条目的直接表（DT），以及一个或多个模式搜索控制块（PSCB），每个具有2个

25. 发明授权

US07899069B2 Priority based bandwidth allocation within real-time and non-real-time traffic streams 失效
标题翻译：实时和非实时业务流中基于优先级的带宽分配
公开(公告)号：US07899069B2
公开(公告)日：2011-03-01
申请号：US12114767
申请日：2008-05-03
申请人： Brahmanand Kumar Gorti , Marco Heddes , Clark Debs Jeffries , Andreas Kind , Michael Steven Siegel
发明人： Brahmanand Kumar Gorti , Marco Heddes , Clark Debs Jeffries , Andreas Kind , Michael Steven Siegel
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L47/6215 , H04L47/10 , H04L47/2416 , H04L47/2433 , H04L47/30 , H04L47/32 , H04L47/50 , H04L47/52 , H04L47/56
摘要： A method and system for transmitting packets in a packet switching network. Packets received by a packet processor may be prioritized based on the urgency to process them. Packets that are urgent to be processed may be referred to as real-time packets. Packets that are not urgent to be processed may be referred to as non-real-time packets. Real-time packets have a higher priority to be processed than non-real-time packets. A real-time packet may either be discarded or transmitted into a real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time queue congestion conditions. A non-real-time packet may either be discarded or transmitted into a non-real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time and non-real-time queue congestion conditions.
摘要翻译：一种用于在分组交换网络中传送分组的方法和系统。可以基于处理它们的紧急性来优先考虑由分组处理器接收的分组。紧急处理的数据包可以称为实时数据包。不紧急处理的数据包可能被称为非实时数据包。实时数据包的优先级要高于非实时数据包。可以根据其值优先级，该值优先级的最小和最大速率以及当前实时队列拥塞条件，将实时分组丢弃或传输到实时队列中。可以基于其值优先级，该值优先级的最小和最大速率以及当前的实时和非实时队列拥塞将非实时分组丢弃或发送到非实时队列条件。

26. 发明申请

US20100191814A1 System-On-A-Chip Employing A Network Of Nodes That Utilize Receive Side Flow Control Over Channels For Messages Communicated Therebetween 审中-公开
标题翻译：系统级芯片采用利用接收侧流控制的节点网络对于其间通信的消息
公开(公告)号：US20100191814A1
公开(公告)日：2010-07-29
申请号：US12639326
申请日：2009-12-16
申请人： Marco Heddes , Massimo Ravasi , Rakesh Kumar Malik , Michael Singngee Yeo
发明人： Marco Heddes , Massimo Ravasi , Rakesh Kumar Malik , Michael Singngee Yeo
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： An integrated circuit an array of nodes linked by an on-chip communication network. Messages are communicated between nodes utilizing logical channels representing hardware resources at the associated nodes. A given logical channel is associated with a receiver node and a transmitter node. The receiver node is adapted to send flow control messages to the transmitter node. The flow control messages include credits that identify hardware resources of the receiver node that are available for receiving messages over the given logical channel. The transmitter node is adapted to maintain a running total of the credits included as part of the flow control messages communicated from the receiver node and to initiate transmission of messages to the receiver node in accordance with the running total of credits maintained at the transmitter node. In the preferred embodiment, the transmitter node is adapted to initiate transmission of a message to the receiver node only if the total number of credits maintained at the transmitter node is sufficient to store the message at the receiver node. A given credit can include an address generated by a receiver node and representing an address in the local memory of the receiver node for storing data. The transmitter node transmits the address of the given credit to the receiver node for storing data therein.
摘要翻译：集成电路，由片上通信网络链接的节点阵列。使用表示相关节点处的硬件资源的逻辑信道在节点之间传送消息。给定的逻辑信道与接收机节点和发射机节点相关联。接收机节点适于向发射机节点发送流量控制消息。流控制消息包括识别接收机节点的硬件资源的信用，该硬件资源可用于通过给定逻辑信道接收消息。发射机节点适于维持作为从接收机节点传送的流控制消息的一部分包括的信用的运行总计，并且根据在发射机节点处保持的信用的运行总计来发起消息到接收机节点的传输。在优选实施例中，只有在发射机节点处保存的信用总数足以在接收机节点处存储消息时，发射机节点适于发起消息到接收机节点的传输。给定的信用可以包括由接收器节点生成的地址并且表示用于存储数据的接收器节点的本地存储器中的地址。发射机节点将给定信用的地址发送到接收机节点，用于在其中存储数据。

27. 发明申请

US20100158005A1 System-On-a-Chip and Multi-Chip Systems Supporting Advanced Telecommunication Functions 审中-公开
标题翻译：支持高级电信功能的片上系统和多芯片系统
公开(公告)号：US20100158005A1
公开(公告)日：2010-06-24
申请号：US12342625
申请日：2008-12-23
申请人： Suvhasis Mukhopadhyay , Marco Heddes , Massimo Ravasi , Michael Singngee Yeo
发明人： Suvhasis Mukhopadhyay , Marco Heddes , Massimo Ravasi , Michael Singngee Yeo
IPC分类号： H04L12/56
CPC分类号： H04L49/109
摘要： A system-on-chip integrated circuit (and multi-chip systems based thereon) that includes a bridge interface that provides transparent bridging of data communicated between integrated circuits.
摘要翻译：一种片上系统集成电路（以及基于其的多芯片系统），其包括提供集成电路之间传送的数据的透明桥接的桥接口。

28. 发明授权

US07490101B2 Method and structure for deleting leaves in tree table structures 失效
标题翻译：在树表结构中删除树叶的方法和结构
公开(公告)号：US07490101B2
公开(公告)日：2009-02-10
申请号：US11462404
申请日：2006-08-04
申请人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall , Sonia K. Rovner
发明人： Claude Basso , Jean L. Calvignac , Gordon T. Davis , Marco Heddes , Piyush C. Patel , Steven R. Perrin , Grayson W. Randall , Sonia K. Rovner
IPC分类号： G06F7/00 , G06F17/00 , G06F17/30
CPC分类号： G06F17/30625 , Y10S707/99936 , Y10S707/99942 , Y10S707/99943
摘要： A technique is provided to delete a leaf from a Patricia tree having a direct table and a plurality of PSCB's which decode portions of the pattern of a leaf in the tree without shutting down the functioning of the tree. A leaf having a pattern is identified as a leaf to be deleted. Using the pattern, the tree is walked to identify the location of the leaf to be deleted. The leaf to be deleted is identified and deleted, and any relevant PSCB modified, if necessary. The technique also is applicable to deleting a prefix of a prefix.
摘要翻译：提供一种技术来从具有直接表的帕特里夏树和多个PSCB中删除叶，该PSCB解码树中的叶的图案的部分，而不关闭树的功能。具有图案的叶被识别为要被删除的叶。使用图案，树被移动以识别要删除的叶子的位置。要删除的叶被识别和删除，并且必要时修改任何相关的PSCB。该技术也适用于删除前缀的前缀。

29. 发明授权

US06910092B2 Chip to chip interface for interconnecting chips 失效
标题翻译：用于互连芯片的芯片到芯片接口
公开(公告)号：US06910092B2
公开(公告)日：2005-06-21
申请号：US10016800
申请日：2001-12-10
申请人： Jean Louis Calvignac , Marco Heddes , Kerry Christopher Imming , Joseph Franklin Logan , Tolga Ozguner
发明人： Jean Louis Calvignac , Marco Heddes , Kerry Christopher Imming , Joseph Franklin Logan , Tolga Ozguner
IPC分类号： G06F13/00 , G06F13/14 , G06F13/42
CPC分类号： G06F13/4265
摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure. Communications between the chips are provided by a pair of Chip to Chip Macros, one of each operatively positioned on one of the chips, and a Chip to Chip Bus Interface operatively coupling the Chip to Chip Macros.
摘要翻译：网络处理器（NP）由多个可操作耦合的芯片形成。 NP包括耦合到耦合到数据流芯片的数据流芯片和数据存储存储器的网络处理器复合（NPC）芯片。可选的调度器芯片耦合到数据流芯片。命名的组件被复制以创建对称的入口和出口结构。芯片之间的通信由一对芯片到芯片宏提供，其中每一个可操作地位于一个芯片上，并且芯片到芯片总线接口可操作地将芯片连接到芯片宏。

30. 发明授权

US07872968B2 Priority based bandwidth allocation within real-time and non-real time traffic streams 有权
标题翻译：实时和非实时业务流中基于优先级的带宽分配
公开(公告)号：US07872968B2
公开(公告)日：2011-01-18
申请号：US11608295
申请日：2006-12-08
申请人： Brahmanand Kumar Gorti , Marco Heddes , Clark Debs Jeffries , Andreas Kind , Michael Steven Siegel
发明人： Brahmanand Kumar Gorti , Marco Heddes , Clark Debs Jeffries , Andreas Kind , Michael Steven Siegel
IPC分类号： G01R31/08 , H04L12/28
CPC分类号： H04L47/6215 , H04L47/10 , H04L47/2416 , H04L47/2433 , H04L47/30 , H04L47/32 , H04L47/50 , H04L47/52 , H04L47/56
摘要： A method and system for transmitting packets in a packet switching network. Packets received by a packet processor may be prioritized based on the urgency to process them. Packets that are urgent to be processed may be referred to as real-time packets. Packets that are not urgent to be processed may be referred to as non-real-time packets. Real-time packets have a higher priority to be processed than non-real-time packets. A real-time packet may either be discarded or transmitted into a real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time queue congestion conditions. A non-real-time packet may either be discarded or transmitted into a non-real-time queue based upon its value priority, the minimum and maximum rates for that value priority and the current real-time and non-real-time queue congestion conditions.
摘要翻译：一种用于在分组交换网络中传送分组的方法和系统。可以基于处理它们的紧急性来优先考虑由分组处理器接收的分组。紧急处理的数据包可以称为实时数据包。不紧急处理的数据包可能被称为非实时数据包。实时数据包的优先级要高于非实时数据包。可以根据其值优先级，该值优先级的最小和最大速率以及当前实时队列拥塞条件，将实时分组丢弃或传输到实时队列中。可以基于其值优先级，该值优先级的最小和最大速率以及当前的实时和非实时队列拥塞将非实时分组丢弃或发送到非实时队列条件。

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