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21. 发明授权

US07228520B1 Method and apparatus for a programmable interface of a soft platform on a programmable logic device 有权
标题翻译：用于可编程逻辑器件上的软平台的可编程接口的方法和装置
公开(公告)号：US07228520B1
公开(公告)日：2007-06-05
申请号：US10769331
申请日：2004-01-30
申请人： Eric R. Keller , Gordon J. Brebner , Philip B. James-Roxby , Chidamber R. Kulkarni
发明人： Eric R. Keller , Gordon J. Brebner , Philip B. James-Roxby , Chidamber R. Kulkarni
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, first attributes are defined for a plurality of threads within the integrated circuit. Second attributes are defined for a memory associated with the integrated circuit. Third attributes are defined for an interconnection topology associated with at least one of the memory and the plurality of threads. Fourth attributes are defined for an interface to at least one of the memory and the plurality of threads.
摘要翻译：描述了用于实现使用集成电路的消息处理系统的可编程架构。在一个示例中，为集成电路内的多个线程定义第一属性。为与集成电路相关联的存储器定义第二属性。为与存储器和多个线程中的至少一个相关联的互连拓扑定义第三属性。为与至少一个存储器和多个线程的接口定义第四属性。

22. 发明授权

US07131077B1 Using an embedded processor to implement a finite state machine 有权
标题翻译：使用嵌入式处理器实现有限状态机
公开(公告)号：US07131077B1
公开(公告)日：2006-10-31
申请号：US10402659
申请日：2003-03-28
申请人： Philip B. James-Roxby , Eric R. Keller
发明人： Philip B. James-Roxby , Eric R. Keller
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Method and System for implementing a Finite State Machine (FSM) using software executed on a processor and having accurate timing information is described, where the accurate timing information is determined without the need to execute the software. An exemplary embodiment includes an IC having an embedded processor and a programmable logic fabric, where part or all of an FSM is implemented using assembly language code stored in a memory, for example, a cache memory, of the embedded processor.
摘要翻译：描述了使用在处理器上执行并具有准确定时信息的软件实现有限状态机（FSM）的方法和系统，其中确定准确的定时信息而不需要执行软件。示例性实施例包括具有嵌入式处理器和可编程逻辑结构的IC，其中使用存储在嵌入式处理器的存储器（例如，高速缓冲存储器）中的汇编语言代码来实现FSM的部分或全部。

23. 发明授权

US07076596B1 Method of and apparatus for enabling a hardware module to interact with a data structure 有权
标题翻译：用于使得硬件模块能够与数据结构交互的方法和装置
公开(公告)号：US07076596B1
公开(公告)日：2006-07-11
申请号：US10354493
申请日：2003-01-30
申请人： Eric R. Keller , Philip B. James-Roxby
发明人： Eric R. Keller , Philip B. James-Roxby
IPC分类号： G06F12/00
CPC分类号： G06F12/0223
摘要： A method of enabling a hardware module to interact with a data structure is disclosed. The method comprises the steps of enabling the hardware module to determine an address of a data item referenced by the data structure; providing a base address for the data structure to the hardware module; and accessing a data item referenced by the data structure. A field programmable gate array having a hardware module capable of interacting with a data structure is also described. The field programmable gate array comprises a memory having a data structure; a hardware module coupled to the memory and comprising a lookup table; and a target address generated by the hardware module for a data item of the data structure.
摘要翻译：公开了一种使得硬件模块能够与数据结构交互的方法。该方法包括以下步骤：使得硬件模块能够确定由数据结构引用的数据项的地址; 为硬件模块提供数据结构的基址; 并访问由数据结构引用的数据项。还描述了具有能够与数据结构交互的硬件模块的现场可编程门阵列。现场可编程门阵列包括具有数据结构的存储器; 耦合到所述存储器并且包括查找表的硬件模块; 以及由硬件模块为数据结构的数据项产生的目标地址。

24. 发明授权

US08122239B1 Method and apparatus for initializing a system configured in a programmable logic device 有权
标题翻译：用于初始化可编程逻辑器件中配置的系统的方法和装置
公开(公告)号：US08122239B1
公开(公告)日：2012-02-21
申请号：US12208452
申请日：2008-09-11
申请人： Philip B. James-Roxby , Stephen A. Neuendorffer , Henry E. Styles
发明人： Philip B. James-Roxby , Stephen A. Neuendorffer , Henry E. Styles
IPC分类号： G01R31/28 , G06F15/177 , G06F11/30 , G06F15/16 , G06F9/30 , G06F7/38
CPC分类号： H03K19/177
摘要： Method and apparatus for initializing a system configured in a programmable logic device (PLD) is described. In some examples, the method includes: initializing memory elements in the system with first data; executing a first iteration of the system to process the first data; partially reconfiguring the PLD, during execution of the first iteration, to initialize shadow memory elements in the PLD with second data, the shadow memory elements respectively shadowing the memory elements in the system; transferring the second data from the shadow memory elements to the memory elements; and executing a second iteration of the system to process the second data.
摘要翻译：描述用于初始化可编程逻辑器件（PLD）中配置的系统的方法和装置。在一些示例中，该方法包括：利用第一数据初始化系统中的存储器元件; 执行所述系统的第一迭代以处理所述第一数据; 在第一次迭代的执行期间，部分地重新配置PLD以利用第二数据初始化PLD中的影子存储器元件，阴影存储器元件分别遮蔽系统中的存储器元件; 将所述第二数据从所述影子存储器元件传送到所述存储器元件; 以及执行所述系统的第二次迭代以处理所述第二数据。

25. 发明授权

US07552405B1 Methods of implementing embedded processor systems including state machines 有权
标题翻译：实现包括状态机的嵌入式处理器系统的方法
公开(公告)号：US07552405B1
公开(公告)日：2009-06-23
申请号：US11880723
申请日：2007-07-24
申请人： Philip B. James-Roxby
发明人： Philip B. James-Roxby
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5027
摘要： Methods of implementing state machines using embedded processors. The designer specifies the logical footprint of the state machine in a formalism that can be transformed into hardware. This approach decouples the designer from the design, so that a state machine can be moved between embedded processors (e.g., between a hard processor and a soft processor), without any modifications to the code. One or more source-to-source transformations can be performed to improve the run-time performance of the state machine. These transformations can include the insertion of one or more jump addresses directly into the code, bypassing the standard lookup table approach for memory addressing, and consequently speeding up the execution of the code. The jump addresses can include, for example, a jump address for the start of each state machine, and/or a jump address for each state within the state machines.
摘要翻译：使用嵌入式处理器实现状态机的方法。设计者以可以转换成硬件的形式化方式指定状态机的逻辑足迹。这种方法使设计人员脱离了设计，使得状态机可以在嵌入式处理器（例如，硬处理器和软处理器之间）之间移动，而不对代码进行任何修改。可以执行一个或多个源到源转换，以改善状态机的运行时性能。这些转换可以包括将一个或多个跳转地址直接插入到代码中，绕过用于存储器寻址的标准查找表方法，从而加速代码的执行。跳转地址可以包括例如每个状态机的启动的跳转地址和/或状态机内的每个状态的跳转地址。

26. 发明授权

US07949790B1 Machines for inserting or removing fixed length data at a fixed location in a serial data stream 有权
标题翻译：用于在串行数据流中的固定位置插入或移除固定长度数据的机器
公开(公告)号：US07949790B1
公开(公告)日：2011-05-24
申请号：US12268674
申请日：2008-11-11
申请人： Philip B. James-Roxby , Gordon J. Brebner , Michael E. Attig
发明人： Philip B. James-Roxby , Gordon J. Brebner , Michael E. Attig
IPC分类号： G06F15/16 , H04J3/00
CPC分类号： H04L69/03 , H04L69/12
摘要： A method of modifying a data stream (12) in an integrated circuit (“IC”) determines a modification point (14) in the data stream from a beginning (16) of the data stream. The modification point is within a word (W7) and has an offset (oww) from the beginning of the word. Data is removed (18) or added (24) to produce a modified data stream (20).
摘要翻译：在集成电路（“IC”）中修改数据流（12）的方法从数据流的开头（16）确定数据流中的修改点（14）。修改点在单词（W7）内，并且具有与单词开头的偏移量（oww）。数据被删除（18）或添加（24）以产生修改的数据流（20）。

27. 发明授权

US07139995B1 Integration of a run-time parameterizable core with a static circuit design 有权
标题翻译：集成一个运行时参数化的核心与静态电路设计
公开(公告)号：US07139995B1
公开(公告)日：2006-11-21
申请号：US10102585
申请日：2002-03-19
申请人： Philip B. James-Roxby , Daniel J. Downs , Russell J. Morgan , Cameron D. Patterson
发明人： Philip B. James-Roxby , Daniel J. Downs , Russell J. Morgan , Cameron D. Patterson
IPC分类号： G06F17/50 , H03K19/173
CPC分类号： G06F17/5054
摘要： Method and apparatus for integrating a run-time parameterizable logic core with a static circuit design. A configuration bitstream is generated from a main circuit design that is specified in a hardware description language. The main circuit design includes a first sub-circuit design that specifies a selected subset of resources of the PLD needed by the RTP core and an interface between the RTP core and other parts of the main circuit design. Via execution of a run-time reconfiguration control program, the configuration data that correspond to the first sub-circuit design are replaced with configuration data that implement the RTP core. The run-time reconfiguration program then configures the PLD with the updated configuration bitstream.
摘要翻译：用于将运行时参数化逻辑核与静态电路设计集成的方法和装置。从硬件描述语言指定的主电路设计中生成配置比特流。主电路设计包括第一子电路设计，其指定RTP核心所需的PLD的所选资源子集以及RTP核心与主电路设计的其他部分之间的接口。通过执行运行时重新配置控制程序，将与第一子电路设计相对应的配置数据替换为实施RTP核心的配置数据。运行时重新配置程序然后使用更新的配置比特流配置PLD。

28. 发明授权

US07133978B1 Method and apparatus for processing data stored in a memory shared among a plurality of processors 有权
标题翻译：用于处理存储在多个处理器之间共享的存储器中的数据的方法和装置
公开(公告)号：US07133978B1
公开(公告)日：2006-11-07
申请号：US10600851
申请日：2003-06-19
申请人： Philip B. James-Roxby , Charles A. Ross , Paul R. Schumacher
发明人： Philip B. James-Roxby , Charles A. Ross , Paul R. Schumacher
IPC分类号： G06F12/14
CPC分类号： G06F9/526 , G06F12/1425 , G06F2209/521
摘要： Method and apparatus for processing data stored in a memory shared among a plurality of processors is described. In an example, a semaphore is provided that is associated with a first portion of the memory. Tasks are stored in the first portion of the memory, the tasks being respectively related to data segments stored in a second portion of the memory. A state of the semaphore is determined. Access among the plurality of processors to the first portion of the memory is controlled in response to the state of the semaphore. A task is executed to process a data segment of the data segments in response to a processor of the plurality of processors gaining access to the first portion of the memory.
摘要翻译：描述用于处理存储在多个处理器中共享的存储器中的数据的方法和装置。在一个示例中，提供与存储器的第一部分相关联的信号量。任务存储在存储器的第一部分中，任务分别与存储在存储器的第二部分中的数据段相关。确定信号量的状态。响应于信号量的状态来控制多个处理器之间对存储器的第一部分的访问。执行任务以响应于所述多个处理器的处理器获得对存储器的第一部分的访问来处理数据段的数据段。

29. 发明授权

US06621295B1 Reconfigurable priority encoding 有权
标题翻译：可重新配置的优先级编码
公开(公告)号：US06621295B1
公开(公告)日：2003-09-16
申请号：US10047667
申请日：2002-01-15
申请人： Philip B. James-Roxby , Daniel J. Downs
发明人： Philip B. James-Roxby , Daniel J. Downs
IPC分类号： G06F738
CPC分类号： G06F7/74
摘要： A reconfigurable priority encoding arrangement and method. In various embodiments, the invention identifies, from a plurality of input signals, a highest priority signal that is in a selected state. A priority routing block is implemented on a programmable logic device (PLD). The routing block has a plurality of input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports. A priority encoder is also implemented on the PLD and has input ports respectively coupled to the output ports of the priority routing block. Each input port has a priority relative to others of the input ports. The priority encoder is configured to generate an address signal that identifies the input signal having a highest priority and that is in the selected state.
摘要翻译：可重构优先级编码方案。在各种实施例中，本发明从多个输入信号中识别处于选定状态的最高优先级信号。优先级路由块在可编程逻辑器件（PLD）上实现。路由块具有布置成接收相应输入信号的多个输入端口和分别耦合到输入端口的多个输出端口。优先编码器也在PLD上实现，并且具有分别耦合到优先级路由块的输出端口的输入端口。每个输入端口相对于其他输入端口具有优先级。优先编码器被配置为生成识别具有最高优先级并且处于选择状态的输入信号的地址信号。

30. 发明授权

US08595442B1 Redundantly validating values with a processor and a check circuit 有权
标题翻译：用处理器和检查电路冗余地验证值
公开(公告)号：US08595442B1
公开(公告)日：2013-11-26
申请号：US12947363
申请日：2010-11-16
申请人： Philip B. James-Roxby , Austin H. Lesea
发明人： Philip B. James-Roxby , Austin H. Lesea
IPC分类号： G06F12/16 , G06F11/00
CPC分类号： G06F11/1415 , G06F11/1004
摘要： Methods and systems redundantly validate values that are stored in a memory arrangement. The memory arrangement includes a first port and a second port that provide coherent access to one or more caches in the memory arrangement, and the first and second ports provide this coherent access at the same priority level. An instruction processor verifies that a first expected value matches a first check value calculated from the values as read from the memory arrangement via the first port. A check circuit verifies that a second expected value matches a second check value calculated from the values as read from the memory arrangement via the second port. A recovery operation is performed in response to the first or second expected values not matching the first and second check values, respectively.
摘要翻译：方法和系统冗余验证存储在存储器排列中的值。存储器装置包括提供对存储器装置中的一个或多个高速缓存的相干访问的第一端口和第二端口，并且第一和第二端口以相同的优先级提供这种一致的访问。指令处理器验证第一期望值是否符合从通过第一端口从存储器装置读取的值计算出的第一检查值。检查电路验证第二期望值是否符合从通过第二端口从存储器装置读取的值计算出的第二检查值。响应于分别与第一和第二检查值不匹配的第一或第二预期值执行恢复操作。

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