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21. 发明授权

US08149038B1 Techniques for phase adjustment 有权
标题翻译：相位调整技术
公开(公告)号：US08149038B1
公开(公告)日：2012-04-03
申请号：US12729114
申请日：2010-03-22
申请人： Chiakang Sung , John Henry Bui , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang
发明人： Chiakang Sung , John Henry Bui , Khai Nguyen , Bonnie I. Wang , Xiaobao Wang
IPC分类号： H03H11/16
CPC分类号： H03L7/0814 , H03K2005/00293
摘要： A dynamic phase alignment circuit includes a phase generator circuit having delay-locked loop circuits that generate periodic output signals. Each of the delay-locked loop circuits generates one of the periodic output signals in response to at least two periodic input signals. A multiplexer circuit selects a selected periodic signal from among the periodic input signals and the periodic output signals based on select signals. A phase detection circuit compares a phase of the selected periodic signal to a data signal to generate a phase detection signal. A control logic circuit generates the select signals. The control logic circuit adjusts the select signals based on changes in the phase detection signal to cause the multiplexer circuit to adjust the phase of the selected periodic signal.
摘要翻译：动态相位对准电路包括具有产生周期性输出信号的延迟锁定环路电路的相位发生器电路。每个延迟锁定环路电路响应于至少两个周期性输入信号产生周期性输出信号之一。多路复用器电路基于选择信号从周期性输入信号和周期性输出信号中选择选定的周期信号。相位检测电路将选择的周期信号的相位与数据信号进行比较，以产生相位检测信号。控制逻辑电路产生选择信号。控制逻辑电路基于相位检测信号的变化来调整选择信号，以使多路复用器电路调整所选周期信号的相位。

22. 发明授权

US06798237B1 On-chip impedance matching circuit 有权
标题翻译：片内阻抗匹配电路
公开(公告)号：US06798237B1
公开(公告)日：2004-09-28
申请号：US10044365
申请日：2002-01-11
申请人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen
发明人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen
IPC分类号： H03K1716
CPC分类号： H04L25/0278
摘要： Integrated circuits with on-chip impedance matching techniques, which greatly reduce the number of off-chip resistors that are coupled to the integrated circuit, are provided. On-chip impedance matching circuits of the present invention are associated with each of a plurality of I/O pins on an integrated circuit. Circuitry of the present invention may include a resistor divider that has a resistor and an on-chip transistor. The resistance of the on-chip transistor and a voltage output signal of the resistor divider vary with process, temperature, and voltage of the integrated circuit. The effective channel W/L ratio of the impedance matching circuit changes in response to the voltage output signal of the resistor divider, so that changes in the impedance of the impedance matching circuit caused by the variations in process, temperature, and voltage are minimized.
摘要翻译：提供具有片上阻抗匹配技术的集成电路，其大大减少耦合到集成电路的片外电阻器的数量。本发明的片上阻抗匹配电路与集成电路上的多个I / O引脚中的每一个相关联。本发明的电路可以包括具有电阻器和片上晶体管的电阻分压器。片上晶体管的电阻和电阻分压器的电压输出信号随集成电路的工艺，温度和电压而变化。阻抗匹配电路的有效通道W / L比随着电阻分压器的电压输出信号而变化，使得由过程，温度和电压变化引起的阻抗匹配电路的阻抗变化最小化。

23. 发明授权

US08610462B1 Input-output circuit and method of improving input-output signals 有权
标题翻译：输入输出电路及改善输入输出信号的方法
公开(公告)号：US08610462B1
公开(公告)日：2013-12-17
申请号：US13332730
申请日：2011-12-21
申请人： Xiaobao Wang , Chiakang Sung , Khai Nguyen , Bonnie I. Wang
发明人： Xiaobao Wang , Chiakang Sung , Khai Nguyen , Bonnie I. Wang
IPC分类号： H03K19/094 , H03K19/0175 , H03K3/00 , H03B1/00
CPC分类号： H03K3/356113
摘要： Circuits and techniques for operating an integrated circuit (IC) with a level shifter circuit are disclosed. A level shifter circuit with input and output terminals is operable to shift an input signal that ranges from a ground voltage to a first positive voltage to an output signal that ranges from the ground voltage to a second positive voltage. The level shifter circuit further includes a first kicker transistor having a first source-drain terminal operable to receive a buffered version of the input signal and having a second source-drain terminal coupled to the output terminal. The first kicker transistor may receive gate signals that turn on the first kicker transistor when the input signal is at the ground voltage and may pull the output terminal to the first positive voltage as the input signal transitions from the ground voltage to the first positive voltage.
摘要翻译：公开了用于利用电平移位器电路来操作集成电路（IC）的电路和技术。具有输入和输出端子的电平移位器电路可操作以将从地电压到第一正电压的输入信号移动到范围从接地电压到第二正电压的输出信号。电平移位器电路还包括具有第一源极 - 漏极端子的第一汲取晶体管，第一源极 - 漏极端子可操作以接收缓冲版本的输入信号并具有耦合到输出端子的第二源极 - 漏极端子。当输入信号处于接地电压时，第一icker晶体晶体管可以接收导通第一猝发晶体管的栅极信号，并且当输入信号从接地电压转变到第一正电压时，可以将输出端拉至第一正电压。

24. 发明授权

US07973553B1 Techniques for on-chip termination 有权
标题翻译：片上终止技术
公开(公告)号：US07973553B1
公开(公告)日：2011-07-05
申请号：US12721759
申请日：2010-03-11
申请人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen , John Henry Bui
发明人： Xiaobao Wang , Chiakang Sung , Bonnie I. Wang , Khai Nguyen , John Henry Bui
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H04L25/0278
摘要： A circuit includes first transistors and a comparator. The comparator compares a reference signal and a signal that is based on conductive states of the first transistors. A control circuit generates first control signals based on an output signal of the comparator. The conductive states of the first transistors are determined based on the first control signals. An arithmetic circuit performs an arithmetic function based on the first control signals and second control signals to generate calibration signals. Second transistors provide a termination impedance at an external terminal of the circuit that is based on the calibration signals.
摘要翻译：电路包括第一晶体管和比较器。比较器比较参考信号和基于第一晶体管的导电状态的信号。控制电路根据比较器的输出信号产生第一控制信号。基于第一控制信号来确定第一晶体管的导通状态。算术电路基于第一控制信号和第二控制信号执行运算功能，以生成校准信号。第二晶体管在基于校准信号的电路的外部端子处提供终端阻抗。

25. 发明授权

US07551014B1 Differential output with low output skew 失效
标题翻译：差分输出具有低输出偏移
公开(公告)号：US07551014B1
公开(公告)日：2009-06-23
申请号：US11670109
申请日：2007-02-01
申请人： Bonnie I. Wang , Chiakang Sung , Khai Nguyen , Xiaobao Wang
发明人： Bonnie I. Wang , Chiakang Sung , Khai Nguyen , Xiaobao Wang
IPC分类号： G06F7/44
CPC分类号： H04L25/0272
摘要： Circuits and methods provide single-ended and differential signals. Single-ended drivers are used to, e.g., reduce pin capacitance. The output cell uses an inversion circuit, such as a phase splitter, to derive the differential signals from the same output signal and provide low skew between the differential signals at the output pins. Selection circuits are used to select between single-ended and differential output.
摘要翻译：电路和方法提供单端和差分信号。单端驱动器用于例如降低引脚电容。输出单元使用诸如分相器的反相电路从相同的输出信号导出差分信号，并在输出引脚之间的差分信号之间提供低偏差。选择电路用于在单端和差分输出之间进行选择。

26. 发明授权

US09099999B1 Adjustable drive strength input-output buffer circuitry 有权
标题翻译：可调驱动强度输入输出缓冲电路
公开(公告)号：US09099999B1
公开(公告)日：2015-08-04
申请号：US13485768
申请日：2012-05-31
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Tony Ngai , Zhe Li , Hong Shi
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Tony Ngai , Zhe Li , Hong Shi
IPC分类号： H01L29/73 , H01L29/40 , H03K17/00 , H05K1/18 , H01L25/065 , H01L27/06
CPC分类号： H03K17/00 , H01L25/0652 , H01L25/0657 , H01L27/0688 , H01L2224/16145 , H01L2224/16225 , H01L2924/0002 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H05K1/144 , H05K1/181 , H05K2201/045 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H01L2924/00
摘要： An integrated circuit in a multi-chip package is provided. The integrated circuit may include adjustable interface circuitry configured to interface with other off-chip components. In particular, the adjustable interface circuitry may include a microbump input-output buffer operable to drive signals off of the integrated circuit and operable to receive signals from other integrated circuits in the multi-chip package via a microbump. The microbump input-output buffer may include output buffers and input buffers. The output buffers may have programmable drive strengths and may each be selectively switched in and out of use depending on the desired application. Each output buffer may include a level shifter, a buffer circuit, and multiple inverter-like circuits each of which can be turned on or off to adjust the drive strength of that output buffer.
摘要翻译：提供了一种多芯片封装中的集成电路。该集成电路可以包括被配置为与其它片外部件接口的可调节接口电路。特别地，可调接口电路可以包括微控制输入 - 输出缓冲器，其可操作用于驱动离开集成电路的信号，并且可操作以经由微型小型接收器从多芯片封装中的其他集成电路接收信号。微控制输入 - 输出缓冲器可以包括输出缓冲器和输入缓冲器。输出缓冲器可以具有可编程驱动强度，并且可以根据期望的应用选择性地切换和使用。每个输出缓冲器可以包括电平移位器，缓冲电路和多个类似逆变器的电路，每个可以导通或关断以调整该输出缓冲器的驱动强度。

27. 发明申请

US20110227606A1 PROGRAMMABLE HIGH-SPEED INTERFACE 有权
标题翻译：可编程高速接口
公开(公告)号：US20110227606A1
公开(公告)日：2011-09-22
申请号：US13149168
申请日：2011-05-31
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03K19/0175 , H03K3/00
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

28. 发明申请

US20080186056A1 PROGRAMMABLE HIGH-SPEED INTERFACE 有权
标题翻译：可编程高速接口
公开(公告)号：US20080186056A1
公开(公告)日：2008-08-07
申请号：US11830831
申请日：2007-07-30
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03K19/0175
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相当简单，在一个示例中，仅具有用于控制线路输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

29. 发明申请

US20100045349A1 PROGRAMMABLE HIGH-SPEED INTERFACE 审中-公开
标题翻译：可编程高速接口
公开(公告)号：US20100045349A1
公开(公告)日：2010-02-25
申请号：US12539606
申请日：2009-08-11
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03K3/00
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

30. 发明授权

US07200769B1 Self-compensating delay chain for multiple-date-rate interfaces 有权
标题翻译：多速率接口的自补偿延迟链
公开(公告)号：US07200769B1
公开(公告)日：2007-04-03
申请号：US10037861
申请日：2002-01-02
申请人： Yan Chong , Chiakang Sung , Bonnie I. Wang , Joseph Huang , Xiaobao Wang , Philip Pan , Tzung-Chin Chang
发明人： Yan Chong , Chiakang Sung , Bonnie I. Wang , Joseph Huang , Xiaobao Wang , Philip Pan , Tzung-Chin Chang
IPC分类号： G06F1/04
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C2207/108 , H03L7/0805 , H03L7/0814 , H03L7/091
摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.
摘要翻译：用于延迟多数据速率接口的时钟信号的方法和装置。一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

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