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21. 发明申请

US20090172429A1 POWER MODE CONTROL METHOD AND CIRCUITRY 有权
标题翻译：电源模式控制方法和电路
公开(公告)号：US20090172429A1
公开(公告)日：2009-07-02
申请号：US11967920
申请日：2007-12-31
申请人： Ramana Rachakonda , Blaise Fanning , Anil K. Sabbavarapu , Belliappa M. Kuttanna , Rajesh Patel , Kenneth D. Shoemaker , Lance E. Hacking , Bruce L. Fleming , Ashish V. Choubal
发明人： Ramana Rachakonda , Blaise Fanning , Anil K. Sabbavarapu , Belliappa M. Kuttanna , Rajesh Patel , Kenneth D. Shoemaker , Lance E. Hacking , Bruce L. Fleming , Ashish V. Choubal
IPC分类号： G06F1/26
CPC分类号： G06F1/3203
摘要： In some embodiments, a power up (or power mode) interface is provided whereby a chip's power up signals are encoded into multiple states to provide more functions than the number of signals used to define the states.
摘要翻译：在一些实施例中，提供上电（或功率模式）接口，由此芯片的上电信号被编码为多个状态以提供比用于定义状态的信号的数量更多的功能。

22. 发明申请

US20080162766A1 SIGNAL TECHNIQUES FOR BUS INTERFACES 审中-公开
标题翻译：总线接口信号技术
公开(公告)号：US20080162766A1
公开(公告)日：2008-07-03
申请号：US11618509
申请日：2006-12-29
申请人： Blaise Fanning , Chris Matthews , Chunyu Zhang
发明人： Blaise Fanning , Chris Matthews , Chunyu Zhang
IPC分类号： G06F13/14
CPC分类号： G06F13/4072 , Y02D10/14 , Y02D10/151
摘要： Techniques involving the transfer of signals across interconnection media are disclosed. For instance, an apparatus may include a configuration module and a driver module. The configuration module establishes an operational mode setting from a first operational mode and a second operational mode. The driver module may operate according to this setting. For instance, according to the first operational mode, the driver module continually drives an interconnection medium. However, for the second operational mode, the driver module drives the interconnection medium when it receives an input signal and otherwise refrains from driving the interconnection medium. According to the first operational mode, a termination module may couple a pull-up resistance to the interconnection medium. However, for the second operational mode, the termination module does not couple such a resistance to the interconnection medium.
摘要翻译：公开了涉及通过互连介质传送信号的技术。例如，设备可以包括配置模块和驱动器模块。配置模块从第一操作模式和第二操作模式建立操作模式设置。驱动器模块可以根据此设置进行操作。例如，根据第一操作模式，驱动器模块连续驱动互连介质。然而，对于第二操作模式，当接收到输入信号并且禁止驱动互连介质时，驱动器模块驱动互连介质。根据第一操作模式，终端模块可以将上拉电阻耦合到互连介质。然而，对于第二操作模式，终端模块不将这种电阻耦合到互连介质。

23. 发明申请

US20060117144A1 Method and apparatus for optimizing data streaming in a computer system utilizing random access memory in a system logic device 有权
标题翻译：用于在系统逻辑设备中利用随机存取存储器的计算机系统中优化数据流的方法和装置
公开(公告)号：US20060117144A1
公开(公告)日：2006-06-01
申请号：US11326997
申请日：2006-01-03
申请人： Blaise Fanning
发明人： Blaise Fanning
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： An apparatus and a method for optimizing data streaming in a computer system utilizing random access memory in a system logic device have been presented. In one embodiment, the apparatus includes a processor interface unit and a cache to store information received from a processor coupled to the processor interface unit, the cache to store disposable information that may be overwritten without ever having delivered the disposable information to a system memory if the disposable information has been read at least once, the processor interface unit to receive a disposable information attribute indication from the processor when the processor delivers the disposable information to the processor interface unit.
摘要翻译：已经提出了一种在系统逻辑设备中利用随机存取存储器来优化计算机系统中的数据流的装置和方法。在一个实施例中，该装置包括处理器接口单元和高速缓存，用于存储从耦合到处理器接口单元的处理器接收到的信息，该高速缓存用于存储可被覆盖的一次性信息，而无需将一次性信息传送到系统存储器，如果该一次性信息已经被读取至少一次，处理器接口单元在处理器将一次性信息提供给处理器接口单元时从处理器接收一次性信息属性指示。

24. 发明授权

US09958926B2 Method and system for providing instant responses to sleep state transitions with non-volatile random access memory 有权
公开(公告)号：US09958926B2
公开(公告)日：2018-05-01
申请号：US13976903
申请日：2011-12-13
申请人： Leena K. Puthiyedath , Raj K. Ramanujan , Michael Rothman , Blaise Fanning , Vincent J. Zimmer
发明人： Leena K. Puthiyedath , Raj K. Ramanujan , Michael Rothman , Blaise Fanning , Vincent J. Zimmer
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： A non-volatile random access memory (NVRAM) is used in a computer system to provide instant responses to sleep state transitions. The computer system includes a processor coupled to an NVRAM, which is accessible by the processor without passing through an I/O subsystem. The NVRAM is byte-rewritable and byte-erasable by the processor. In response to a request to enter a powered sleep state, the computer system converts the powered sleep state into a powered-off sleep state with system memory context stored in the NVRAM. The powered sleep state is defined as a state in which power is supplied to volatile random access memory in the computer system, and the powered-off sleep state is defined as a state in which power is removed from the volatile random access memory. In response to a wake event, the computer system resumes working state operations using the system memory context stored in the NVRAM.

25. 发明申请

US20150032941A1 NON-VOLATILE MEMORY INTERFACE 有权
标题翻译：非易失性存储器接口
公开(公告)号：US20150032941A1
公开(公告)日：2015-01-29
申请号：US14128669
申请日：2013-07-25
申请人： Eng Hun Ooi , Robert J. Royer, JR. , Michael W. Williams , Jeffrey R. Wilcox , Ritesh B. Trivedi , Blaise Fanning
发明人： Eng Hun Ooi , Robert J. Royer, JR. , Michael W. Williams , Jeffrey R. Wilcox , Ritesh B. Trivedi , Blaise Fanning
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0679 , G06F12/02 , G06F13/12 , G06F13/16 , G06F13/1668 , G06F13/38 , G06F13/4234 , G06F2212/7202
摘要： In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a point-to-point bus between a memory interface and the non-volatile memory. The memory interface may send the request to the non-volatile memory via the bus. The request may include an address that may be used to identify a location for storing or reading data. The non-volatile memory may acquire the request from the bus and process the request. After processing the request, the non-volatile memory may send an indication to the memory interface that indicates the non-volatile memory has a response to send to the memory interface. The memory interface may grant access to the bus to the non-volatile memory. After being granted access to the bus, the non-volatile memory may send the response to the memory interface.
摘要翻译：在一个实施例中，存储器接口可以发送请求被发送的指示。该指示可以经由存储器接口和非易失性存储器之间的点对点总线发送到非易失性存储器。存储器接口可以经由总线将请求发送到非易失性存储器。请求可以包括可用于标识用于存储或读取数据的位置的地址。非易失性存储器可以从总线获取请求并处理请求。在处理请求之后，非易失性存储器可以向存储器接口发送指示非易失性存储器具有发送到存储器接口的响应的指示。存储器接口可以向总线授予对非易失性存储器的访问。在被允许访问总线之后，非易失性存储器可以将响应发送到存储器接口。

26. 发明申请

US20150012681A1 Common Idle State, Active State And Credit Management For An Interface 审中-公开
标题翻译：通用空闲状态，活动状态和信用管理接口
公开(公告)号：US20150012681A1
公开(公告)日：2015-01-08
申请号：US14326654
申请日：2014-07-09
申请人： Sridhar Lakshmanamurthy , Robert P. Adler , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Rohit R. Verma
发明人： Sridhar Lakshmanamurthy , Robert P. Adler , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Rohit R. Verma
IPC分类号： G06F13/42 , G06F9/46
CPC分类号： G06F13/42 , G06F9/466 , G06F15/7825 , G06F15/7864 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： In one embodiment, the present invention includes method for entering a credit initialization state of an agent state machine of an agent coupled to a fabric to initialize credits in a transaction credit tracker of the fabric. This tracker tracks credits for transaction queues of a first channel of the agent for a given transaction type. The agent may then assert a credit initialization signal to cause credits to be stored in the transaction credit tracker corresponding to the number of the transaction queues of the first channel of the agent for the first transaction type. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括用于输入耦合到结构的代理的代理状态机的信用初始化状态以便初始化该结构的交易信用跟踪器中的信用的方法。该跟踪器跟踪给定交易类型的代理的第一渠道的交易队列的信用。然后，代理可以断言信用初始化信号，以使得信用被存储在与第一交易类型的代理的第一渠道的交易队列的数量相对应的交易信用跟踪器中。描述和要求保护其他实施例。

27. 发明授权

US08874976B2 Providing error handling support to legacy devices 有权
标题翻译：为传统设备提供错误处理支持
公开(公告)号：US08874976B2
公开(公告)日：2014-10-28
申请号：US13248252
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Rohit R. Verma
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Rohit R. Verma
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0772 , G06F11/0784 , G06F11/0793 , G06F13/4221
摘要： In one embodiment, the present invention includes a method for handling a request received in an agent designed in accordance with a peripheral component interconnect (PCI) specification using PCI Express semantics. More specifically, responsive to determining that the agent does not support the request, an unsupported request detection register of the agent can be updated, and a response sent from the agent to indicate that the agent does not support the request. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种处理在根据使用PCI Express语义的外围组件互连（PCI）规范设计的代理中接收到的请求的方法。更具体地，响应于确定代理不支持请求，可以更新代理的不支持的请求检测注册器，以及从代理发送的指示代理不支持该请求的响应。描述和要求保护其他实施例。

28. 发明申请

US20140289435A1 Issuing Requests To A Fabric 审中-公开
标题翻译：向织物发出请求
公开(公告)号：US20140289435A1
公开(公告)日：2014-09-25
申请号：US14295810
申请日：2014-06-04
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Eran Tamari , Joseph Murray , Kar Leong Wong , Robert P. Adler
IPC分类号： G06F13/366
CPC分类号： G06F13/4221 , G06F13/366 , G06F13/368 , G06F13/4022 , G06F15/7807 , G06F15/7864
摘要： In one embodiment, a method includes determining whether producer-consumer ordering rules have been met for a first transaction to be sent from a source agent to a target agent via a fabric, and if so a first request for the first transaction is sent from the source agent to the fabric in a first clock cycle. Then a second request can be sent from the source agent to the fabric for a second transaction in a pipelined manner. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，一种方法包括确定是否已经通过结构从源代理发送到目标代理的第一事务已经满足生产者 - 消费者排序规则，并且如果是，则从第一事务发送第一事务的第一请求源代理程序在第一个时钟周期。然后，可以以流水线的方式从源代理向结构发送第二请求用于第二事务。描述和要求保护其他实施例。

29. 发明申请

US20130339572A1 MULTI-LEVEL MEMORY WITH DIRECT ACCESS 有权
标题翻译：具有直接访问的多级记忆
公开(公告)号：US20130339572A1
公开(公告)日：2013-12-19
申请号：US13993695
申请日：2011-12-29
申请人： Blaise Fanning , Shekoufeh Qawami , Raymond S. Tetrick , Frank T. Hady
发明人： Blaise Fanning , Shekoufeh Qawami , Raymond S. Tetrick , Frank T. Hady
IPC分类号： G11C7/10
CPC分类号： G06F3/0644 , G06F3/0604 , G06F3/0631 , G06F3/0679 , G06F3/0688 , G06F12/023 , G06F12/0238 , G06F12/0246 , G06F12/08 , G06F12/10 , G06F12/1009 , G06F2212/2024 , G06F2212/205 , G06F2212/7201 , G06F2212/7204 , G11C7/1006 , G11C11/56 , G11C16/00 , Y02D10/13
摘要： Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system.
摘要翻译：公开了用于实现具有直接访问的多级存储器的方法，设备和系统的实施例。在一个实施例中，该方法包括指定要用作动态随机存取存储器（DRAM）的存储器备选方案的计算机系统中的非易失性随机存取存储器（NVRAM）的量。该方法通过指定要用作大容量存储设备的存储备用的第二数量的NVRAM来继续。然后，该方法在计算机系统的操作期间将存储器备选指定中的第一数量的NVRAM的至少第一部分重新指定为存储备选指定。最后，该方法在计算机系统的操作期间将第二数量的NVRAM的至少第一部分从存储替代指定重新指定到存储器备选指定。

30. 发明申请

US20130086433A1 Providing Error Handling Support To Legacy Devices 有权
公开(公告)号：US20130086433A1
公开(公告)日：2013-04-04
申请号：US13248252
申请日：2011-09-29
申请人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Rohit R. Verma
发明人： Sridhar Lakshmanamurthy , Mikal C. Hunsaker , Michael T. Klinglesmith , Blaise Fanning , Rohit R. Verma
IPC分类号： G06F11/07 , G06F13/20
CPC分类号： G06F11/0772 , G06F11/0784 , G06F11/0793 , G06F13/4221
摘要： In one embodiment, the present invention includes a method for handling a request received in an agent designed in accordance with a peripheral component interconnect (PCI) specification using PCI Express™ semantics. More specifically, responsive to determining that the agent does not support the request, an unsupported request detection register of the agent can be updated, and a response sent from the agent to indicate that the agent does not support the request. Other embodiments are described and claimed.

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