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21. 发明授权

US08592269B2 Method of manufacturing gate structure and method of manufacturing semiconductor device including the same 有权
标题翻译：制造栅极结构的方法和制造其的半导体器件的制造方法
公开(公告)号：US08592269B2
公开(公告)日：2013-11-26
申请号：US12942107
申请日：2010-11-09
申请人： Ki-Hyun Hwang , Won-Jun Jang , Jae-Young Ahn , Chang-Sup Mun , Jung-Hyun Park
发明人： Ki-Hyun Hwang , Won-Jun Jang , Jae-Young Ahn , Chang-Sup Mun , Jung-Hyun Park
IPC分类号： H01L21/8238
CPC分类号： B82Y10/00 , H01L21/823425 , H01L21/823462 , H01L27/115 , H01L27/11521
摘要： In a method for manufacturing a semiconductor device, a silicon oxide layer is formed on a substrate. The silicon oxide layer is treated with a solution comprising ozone. Then, a conductive layer is formed on the silicon oxide layer treated with the solution.
摘要翻译：在半导体装置的制造方法中，在基板上形成氧化硅层。氧化硅层用包含臭氧的溶液处理。然后，在用该溶液处理的氧化硅层上形成导电层。

22. 发明授权

US07510935B2 Method of manufacturing a charge-trapping dielectric and method of manufacturing a sonos-type non-volatile semiconductor device 有权
标题翻译：电荷俘获电介质的制造方法和声波型非易失性半导体器件的制造方法
公开(公告)号：US07510935B2
公开(公告)日：2009-03-31
申请号：US11468944
申请日：2006-08-31
申请人： Sung-Hae Lee , Ju-Wan Lim , Jae-Young Ahn , Sang-Ryol Yang , Ki-Hyun Hwang
发明人： Sung-Hae Lee , Ju-Wan Lim , Jae-Young Ahn , Sang-Ryol Yang , Ki-Hyun Hwang
IPC分类号： H01L21/8247
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/4234 , Y10S438/954
摘要： In an embodiment, a method of manufacturing a charge-trapping dielectric and a silicon-oxide-nitride-oxide-silicon (SONOS)-type non-volatile semiconductor device includes forming the charge-trapping dielectric, and a first oxide layer including silicon oxide. A silicon nitride layer including silicon-rich nitride is formed by a cyclic chemical vapor deposition (CVD) process using a silicon source material and a nitrogen source gas. A second oxide layer is formed on the silicon nitride layer. Hence, the charge-trapping dielectric having good erase characteristics is formed. In the SONOS-type non-volatile semiconductor device including the charge-trapping dielectric, a data erase process may be stably performed.
摘要翻译：在一个实施例中，制造电荷俘获电介质和氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体器件的方法包括形成电荷俘获电介质和包含氧化硅的第一氧化物层。通过使用硅源材料和氮源气体的循环化学气相沉积（CVD）工艺形成包括富含硅的氮化物的氮化硅层。在氮化硅层上形成第二氧化物层。因此，形成具有良好擦除特性的电荷俘获电介质。在包含电荷捕获电介质的SONOS型非易失性半导体器件中，可以稳定地执行数据擦除处理。

23. 发明申请

US20070134415A1 Oxidation Treatment Apparatus and Method 审中-公开
标题翻译：氧化处理装置及方法
公开(公告)号：US20070134415A1
公开(公告)日：2007-06-14
申请号：US11563980
申请日：2006-11-28
申请人： Ki-Hyun Hwang , U-In Chung , Yu-Gyun Shin , Jae-Young Ahn , Jin-Gyun Kim
发明人： Ki-Hyun Hwang , U-In Chung , Yu-Gyun Shin , Jae-Young Ahn , Jin-Gyun Kim
IPC分类号： C23C16/00 , B05D3/04 , B05D7/00 , B05D1/02
CPC分类号： H01L21/02233 , H01L21/31654
摘要： An oxidation treatment apparatus for oxidizing a surface of a substrate includes a process chamber for performing a process, a boat supporting the substrate and disposed in the process chamber during the process and a first ozone supply unit supplying ozone to the process chamber. The first ozone supply unit includes an ozone generator disposed at an exterior of the process chamber and an ozone spray nozzle disposed in the process chamber to spray the ozone supplied from the ozone generator into the process chamber.
摘要翻译：用于氧化基板表面的氧化处理装置包括处理过程的处理室，支撑基板的船，并且在处理过程中设置在处理室中，以及向处理室供应臭氧的第一臭氧供给单元。第一臭氧供应单元包括设置在处理室外部的臭氧发生器和设置在处理室中的臭氧喷嘴，以将从臭氧发生器供应的臭氧喷射到处理室中。

24. 发明授权

US09461061B2 Vertical memory devices and methods of manufacturing the same 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US09461061B2
公开(公告)日：2016-10-04
申请号：US14546172
申请日：2014-11-18
申请人： Phil-Ouk Nam , Jun-Kyu Yang , Jin-Gyun Kim , Jae-Young Ahn , Hun Hyeong Lim , Ki-Hyun Hwang
发明人： Phil-Ouk Nam , Jun-Kyu Yang , Jin-Gyun Kim , Jae-Young Ahn , Hun Hyeong Lim , Ki-Hyun Hwang
IPC分类号： H01L27/115 , H01L29/66 , H01L29/792
CPC分类号： H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.
摘要翻译：制造垂直存储器件的方法包括在衬底上形成交替和重复的绝缘夹层和牺牲层，牺牲层包括多晶硅或非晶硅，通过绝缘夹层和牺牲层形成通道孔，在通道孔中形成通道，蚀刻绝缘夹层的部分和相邻通道之间的牺牲层以形成开口，去除牺牲层以在绝缘夹层之间形成间隙，并在间隙中形成栅极线。

25. 发明申请

US20150187790A1 METHODS OF FORMING VERTICAL TYPE SEMICONDUCTOR DEVICES INCLUDING OXIDATION TARGET LAYERS 审中-公开
标题翻译：形成包含氧化目标层的垂直型半导体器件的方法
公开(公告)号：US20150187790A1
公开(公告)日：2015-07-02
申请号：US14643527
申请日：2015-03-10
申请人： Phil-Ouk Nam , Jun-Kyu Yang , Byong-Hyun Jang , Ki-Hyun Hwang , Jae-Young Ahn
发明人： Phil-Ouk Nam , Jun-Kyu Yang , Byong-Hyun Jang , Ki-Hyun Hwang , Jae-Young Ahn
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/7889 , H01L29/7926
摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.
摘要翻译：垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙比第二垂直间隙宽第一垂直间隙。水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

26. 发明授权

US08987805B2 Vertical type semiconductor devices including oxidation target layers 有权
标题翻译：包括氧化靶层的垂直型半导体器件
公开(公告)号：US08987805B2
公开(公告)日：2015-03-24
申请号：US13971347
申请日：2013-08-20
申请人： Phil-Ouk Nam , Jun-Kyu Yang , Byong-Hyun Jang , Ki-Hyun Hwang , Jae-Young Ahn
发明人： Phil-Ouk Nam , Jun-Kyu Yang , Byong-Hyun Jang , Ki-Hyun Hwang , Jae-Young Ahn
IPC分类号： H01L29/792 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/7889 , H01L29/7926
摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.
摘要翻译：垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙宽于第一垂直间隙。水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

27. 发明授权

US09368646B2 Memory devices and methods of manufacturing the same 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US09368646B2
公开(公告)日：2016-06-14
申请号：US14182325
申请日：2014-02-18
申请人： Jin-Gyun Kim , Jae-Young Ahn , Ki-Hyun Hwang
发明人： Jin-Gyun Kim , Jae-Young Ahn , Ki-Hyun Hwang
IPC分类号： H01L27/115 , H01L29/792 , H01L29/66
CPC分类号： H01L29/7926 , H01L27/11582 , H01L29/66833
摘要： A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern, which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is formed on a second region adjacent the first region of the substrate and is formed to extend in the first direction.
摘要翻译：垂直存储器件包括沟道阵列，电荷存储层结构，多个栅电极和虚拟图案阵列。通道阵列包括多个通道，每个通道形成在基板的第一区域上，并且形成为在基本上垂直于基板的顶表面的第一方向上延伸。电荷存储层结构包括隧道绝缘层图案，电荷存储层图案和阻挡层图案，它们在基本上平行于基板的顶表面的第二方向上顺序地形成在每个沟道的侧壁上。所述栅极布置在所述电荷存储层结构的侧壁上并且在所述第一方向上彼此间隔开。虚拟图案阵列包括多个虚设图案，每个虚设图案形成在与基板的第一区域相邻的第二区域上，并且形成为沿第一方向延伸。

28. 发明申请

US20150145021A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20150145021A1
公开(公告)日：2015-05-28
申请号：US14517025
申请日：2014-10-17
申请人： Byong-Hyun Jang , Dong-Chul Yoo , Ki-Hyun Hwang , Phil-Ouk Nam , Jae-Young Ahn
发明人： Byong-Hyun Jang , Dong-Chul Yoo , Ki-Hyun Hwang , Phil-Ouk Nam , Jae-Young Ahn
IPC分类号： H01L27/115 , H01L29/51
CPC分类号： H01L27/11565 , H01L27/1158 , H01L29/66833 , H01L29/7926
摘要： Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.
摘要翻译：非易失性存储器件包括至少四个圆柱形沟道区域，当从垂直于衬底表面的垂直方向观察时，至少四个圆柱形沟道区域从位于至少一个菱形晶体的相应顶点处的衬底的部分垂直延伸。电荷存储层（例如，ONO层）设置在每个圆柱形沟道区的外侧壁上。此外，为了实现高度的集成，提供了多个垂直堆叠的栅电极，其在每个圆柱形沟道区域附近延伸。

29. 发明授权

US08435877B2 Methods of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08435877B2
公开(公告)日：2013-05-07
申请号：US13227799
申请日：2011-09-08
申请人： Jun-Kyu Yang , Hong-Suk Kim , Ju-Yul Lee , Ki-Hyun Hwang , Jae-Young Ahn
发明人： Jun-Kyu Yang , Hong-Suk Kim , Ju-Yul Lee , Ki-Hyun Hwang , Jae-Young Ahn
IPC分类号： H01L21/28
CPC分类号： H01L21/28247 , H01L21/28273 , H01L21/764 , H01L27/11568
摘要： A semiconductor device includes gate structures including a tunnel insulating layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially disposed on a substrate. The control gate includes an impurity doped polysilicon layer pattern and a metal layer pattern. The gate structures are spaced apart from each other on the substrate. A capping layer pattern is disposed on a sidewall portion of the metal layer pattern and includes a metal oxide. An insulating layer covers the gate structures and the capping layer pattern. The insulating layer is formed on the substrate and includes an air-gap therein.
摘要翻译：半导体器件包括栅极结构，其包括顺序地设置在衬底上的隧道绝缘层图案，浮动栅极，电介质层图案和控制栅极。控制栅极包括杂质掺杂多晶硅层图案和金属层图案。栅极结构在衬底上彼此间隔开。覆盖层图案设置在金属层图案的侧壁部分上并且包括金属氧化物。绝缘层覆盖栅极结构和覆盖层图案。绝缘层形成在基板上并且在其中包括气隙。

30. 发明申请

US20120064707A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120064707A1
公开(公告)日：2012-03-15
申请号：US13227799
申请日：2011-09-08
申请人： Jun-Kyu YANG , Hong-Suk Kim , Ju-Yul Lee , Ki-Hyun Hwang , Jae-Young Ahn
发明人： Jun-Kyu YANG , Hong-Suk Kim , Ju-Yul Lee , Ki-Hyun Hwang , Jae-Young Ahn
IPC分类号： H01L21/28
CPC分类号： H01L21/28247 , H01L21/28273 , H01L21/764 , H01L27/11568
摘要： A semiconductor device includes gate structures including a tunnel insulating layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially disposed on a substrate. The control gate includes an impurity doped polysilicon layer pattern and a metal layer pattern. The gate structures are spaced apart from each other on the substrate. A capping layer pattern is disposed on a sidewall portion of the metal layer pattern and includes a metal oxide. An insulating layer covers the gate structures and the capping layer pattern. The insulating layer is formed on the substrate and includes an air-gap therein.
摘要翻译：半导体器件包括栅极结构，其包括顺序地设置在衬底上的隧道绝缘层图案，浮动栅极，电介质层图案和控制栅极。控制栅极包括杂质掺杂多晶硅层图案和金属层图案。栅极结构在衬底上彼此间隔开。覆盖层图案设置在金属层图案的侧壁部分上并且包括金属氧化物。绝缘层覆盖栅极结构和覆盖层图案。绝缘层形成在基板上并且在其中包括气隙。

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