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21. 发明授权

US06794275B2 Process for forming a silicon-based film on a substrate using a temperature gradient across the substrate axis 失效
标题翻译：使用基板轴上的温度梯度在基板上形成硅基膜的工艺
公开(公告)号：US06794275B2
公开(公告)日：2004-09-21
申请号：US10113675
申请日：2002-04-02
申请人： Takaharu Kondo , Shotaro Okabe , Masafumi Sano , Akira Sakai , Yuzo Koda , Ryo Hayashi , Shuichiro Sugiyama , Koichiro Moriyama
发明人： Takaharu Kondo , Shotaro Okabe , Masafumi Sano , Akira Sakai , Yuzo Koda , Ryo Hayashi , Shuichiro Sugiyama , Koichiro Moriyama
IPC分类号： H01L21365
CPC分类号： H01L31/1804 , C23C16/46 , C23C16/463 , C23C16/505 , C23C16/52 , C23C16/545 , H01L21/02422 , H01L21/02425 , H01L21/02491 , H01L21/02505 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L29/66765 , H01L31/075 , H01L31/076 , H01L31/1824 , H01L31/1884 , H01L31/202 , Y02E10/545 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： In a process for forming a silicon-based film on a substrate according to the present invention, the substrate has a temperature gradient in the thickness direction thereof in the formation of the silicon-based film and the temperature gradient is made such that a deposition surface of the substrate has a higher temperature than a backside or the direction of the temperature gradient is reversed. With this configuration, the present invention provides a silicon-based thin film having good properties at a high deposition rate and provides a semiconductor device including it. The present invention also provides a semiconductor device including the silicon-based thin films that has good adhesion and weather-resisting properties and that can be manufactured in a short tact time.
摘要翻译：在根据本发明的基板上形成硅基膜的方法中，在形成硅基膜时，基板在其厚度方向上具有温度梯度，并使温度梯度使得沉积表面的衬底具有比背面更高的温度或温度梯度的方向反转。利用这种结构，本发明提供一种在高沉积速率下具有良好性能的硅基薄膜，并提供包括它的半导体器件。本发明还提供一种半导体器件，其包括硅基薄膜，其具有良好的粘合性和耐候性，并且可以在短的时间内制造。

22. 发明授权

US06737123B2 Silicon-based film formation process, silicon-based film, semiconductor device, and silicon-based film formation system 失效
标题翻译：硅基成膜工艺，硅基膜，半导体器件和硅基成膜体系
公开(公告)号：US06737123B2
公开(公告)日：2004-05-18
申请号：US10166759
申请日：2002-06-12
申请人： Takaharu Kondo , Masafumi Sano , Akira Sakai , Tadashi Sawayama , Ryo Hayashi , Shuichiro Sugiyama , Hiroyuki Ozaki , Yoshinori Sugiura
发明人： Takaharu Kondo , Masafumi Sano , Akira Sakai , Tadashi Sawayama , Ryo Hayashi , Shuichiro Sugiyama , Hiroyuki Ozaki , Yoshinori Sugiura
IPC分类号： C23C16505
CPC分类号： C23C16/517 , H01L21/02422 , H01L21/02425 , H01L21/02491 , H01L21/02505 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L31/02363 , H01L31/02366 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A silicon-based film is formed superimposing a direct-current potential on the high-frequency power to set the potential of the high-frequency power feed section to a potential which is lower by V1 than the ground potential; the V1 satisfying |V2|≦|V1|≦50×|V2|, where V2 is the potential difference from the ground potential, produced in the electrode in the state the plasma has taken place under the same conditions except that the direct-current potential is not superposed on the high-frequency power and the electrode is brought into a non-grounded state. This can provide a silicon-based film having superior characteristics at a high film formation rate, and a semiconductor device making use of this silicon-based film, having superior adherence, environmental resistance, and can enjoy a short tact time at the time of manufacture.
摘要翻译：形成在高频电力上叠加直流电位的硅基膜，将高频供电部的电位设定为比地电位低V1的电位; 满足| V2 | <= | V1 | <= 50x | V2 |的V1，其中V2是在等离子体在相同条件下发生的状态下在电极中产生的与地电位的电位差，电流电势不叠加在高频电源上，并且电极进入非接地状态。这可以提供具有高成膜速度的优异特性的硅基膜和使用该硅基膜的半导体器件，具有优异的附着力，耐环境性，并且可以在制造时享受短的时间。

23. 发明授权

US5236798A Electrophotographic light receiving member having a photoconductive layer formed of non-single crystal silicon material and a surface layer containing polysilane compound 失效
标题翻译：具有由非单晶硅材料形成的光电导层和含有聚硅烷化合物的表面层的电子照相光接收元件
公开(公告)号：US5236798A
公开(公告)日：1993-08-17
申请号：US587990
申请日：1990-09-25
申请人： Tatsuyuki Aoike , Koichi Matsuda , Keishi Saitoh , Mitsuyuki Niwa , Masafumi Sano , Hisami Tanaka
发明人： Tatsuyuki Aoike , Koichi Matsuda , Keishi Saitoh , Mitsuyuki Niwa , Masafumi Sano , Hisami Tanaka
IPC分类号： G03G5/08 , C08G77/60 , C08K3/16 , C08K5/17 , G03F7/075 , G03G5/147 , H01L51/30
CPC分类号： G03F7/0754 , C08G77/60 , C08K3/16 , C08K5/17 , H01L51/0094
摘要： An electrophotographic light receiving member comprising a substrate and a light receiving layer having a multi-layered structure disposed on said substrate, said light receiving layer comprising at least a photoconductive layer and a surface layer being stacked in this order from the side of said substrate, said photoconductive layer being formed of a non-single crystal material containing silicon atoms as the matrix and at least one kind of atoms selected from the group consisting of hydrogen atoms and halogen atoms, and said surface layer being formed of a polysilane compound having a weight average molecular weight of 6000 to 200000 and having at least an oxygen-free organic group selected from the group consisting of alkyl group, cycloalkyl group, aryl group and aralkyl group at the terminals.
摘要翻译：一种电子照相光接收构件，包括基板和设置在所述基板上的具有多层结构的光接收层，所述光接收层至少包含光电导层和从所述基板侧依次堆叠的表面层，所述光电导层由含有硅原子作为基体的非单晶材料和选自氢原子和卤素原子的至少一种原子形成，所述表面层由具有重量的聚硅烷化合物形成平均分子量为6000〜200000，并且在末端具有至少一个选自烷基，环烷基，芳基和芳烷基的无氧有机基团。

24. 发明授权

US5324364A Pin junction photovoltaic device having an i-type a-SiGe semiconductor layer with a maximal point for the Ge content 失效
标题翻译：具有具有Ge含量最大点的i型a-SiGe半导体层的pin结光电器件
公开(公告)号：US5324364A
公开(公告)日：1994-06-28
申请号：US45176
申请日：1993-04-13
申请人： Koichi Matsuda , Masafumi Sano , Tsutomu Murakami
发明人： Koichi Matsuda , Masafumi Sano , Tsutomu Murakami
IPC分类号： H01L31/04 , H01L31/0376 , H01L31/075
CPC分类号： H01L31/076 , H01L31/03765 , H01L31/065 , H01L31/075 , Y02E10/548
摘要： A pin junction photovoltaic device comprising a substrate and a pin junction semiconductor active layer region disposed on said substrate, said pin junction semiconductor active layer region comprising a p-type semiconductor layer composed of a p-type non-single crystalline semiconductor material, an i-type semiconductor layer composed of an i-type non-single crystalline semiconductor material, and an n-type semiconductor layer composed of an n-type non-single crystalline semiconductor material, characterized in that (a) a buffer layer comprising a non-single crystalline silicon semiconductor material substantially free of germanium atoms is interposed between said p-type semiconductor layer and said i-type semiconductor layer, (b) a buffer layer comprising a non-single crystalline silicon semiconductor material substantially free of germanium atoms is interposed between said i-type semiconductor layer and said n-type semiconductor layer, and said i-type semiconductor layer is formed of an amorphous silicon germanium semiconductor material containing the germanium atoms in an amount of 20 to 70 atomic % in the entire region in which the concentration distribution of the germanium atoms in the thickness direction is varied while providing a maximum concentration point.
摘要翻译：一种pin结光电器件，包括衬底和设置在所述衬底上的pin结半导体有源层区域，所述pin结半导体有源层区域包括由p型非单晶半导体材料构成的p型半导体层，i 由n型非单晶半导体材料构成的n型半导体层以及由n型非单晶半导体材料构成的n型半导体层，其特征在于，（a）基本上不含锗原子的单晶硅半导体材料介于所述p型半导体层和所述i型半导体层之间，（b）包含基本上不含锗原子的非单晶硅半导体材料的缓冲层介于所述i型半导体层和所述n型半导体层，并且所述i型半导体层形成为o f是在锗原子在厚度方向上的浓度分布同时提供最大浓度点的整个区域中含有锗原子的含量为20至70原子％的非晶硅锗半导体材料。

25. 发明授权

US5190838A Electrophotographic image-forming member with photoconductive layer comprising non-single-crystal silicon carbide 失效
标题翻译：具有包含非单晶碳化硅的光电导层的电子照相成像部件
公开(公告)号：US5190838A
公开(公告)日：1993-03-02
申请号：US572354
申请日：1990-08-27
申请人： Keishi Saitoh , Masafumi Sano , Koichi Matsuda
发明人： Keishi Saitoh , Masafumi Sano , Koichi Matsuda
IPC分类号： G03G5/082
CPC分类号： G03G5/08214 , G03G5/08221 , G03G5/08235
摘要： An electrophotographic image-forming member which comprises a substrate for electrophotography and a light receiving layer being disposed on said substrate, said light receiving layer comprising a photoconductive layer formed of a non-single-crystal silicon carbide film containing silicon atoms as a matrix, carbon atoms in an amount of 5 to 15 atomic % and hydrogen atoms in an amount of 1 to 10 atomic %, containing graphite structure domains in a proportion of 1% or less per unit volume and having an intensity ratio of 0.01 to 0.05 between the C--H bond stretching mode and the Si--H bond stretching mode in an infrared adsorption spectrum.The light receiving layer may further comprise a charge injection inhibition layer or/and a surface layer.The electrophotographic image-forming member can be used in a high-speed continuous electrophotographic copying systems using a coherent light laser beam as the light source without accompaniment of the problems which are found on conventional amorphous silicon carbide system electrophotographic image-forming members.
摘要翻译：一种电子照相图像形成部件，包括用于电子照相的基板和设置在所述基板上的受光层，所述光接收层包括由含有硅原子作为基体的非单晶碳化硅膜形成的光电导层，碳原子数为5〜15原子％，氢原子为1〜10原子％，含有比例为1％以下的石墨结构域，单位体积的重量比为0.01〜0.05，CH 键拉伸模式和Si-H键拉伸模式在红外吸收光谱中。光接收层还可以包括电荷注入抑制层或/和表面层。电子照相图像形成构件可以用于使用相干光激光束作为光源的高速连续电子照相复印系统，而不伴随在常规非晶碳化硅系统电子照相成像构件上发现的问题。

26. 发明授权

US08599111B2 Driving circuit of display element and image display apparatus 有权
标题翻译：显示元件和图像显示装置的驱动电路
公开(公告)号：US08599111B2
公开(公告)日：2013-12-03
申请号：US12162929
申请日：2007-03-08
申请人： Katsumi Abe , Masafumi Sano , Ryo Hayashi , Hideya Kumomi
发明人： Katsumi Abe , Masafumi Sano , Ryo Hayashi , Hideya Kumomi
IPC分类号： G09G3/30 , G09G5/10
CPC分类号： G09G3/3283 , G09G3/2014 , G09G3/325 , G09G2300/0819 , G09G2300/0852 , G09G2300/0861 , G09G2310/0251 , G09G2310/066 , G09G2320/0238 , G09G2320/043
摘要： A driving circuit of a display element includes a current source circuit having a first transistor and a holding circuit for holding a gate voltage of the first transistor during a first period at an electric potential corresponding to a constant current to be supplied to the display element, and a control circuit including a second transistor connected in series to the current source circuit and connected in parallel to the display element and the capacitor element whose one terminal is connected to a gate of the second transistor and the other terminal is connected to a line, and controlling the light emission time of the display element by controlling the second transistor during a third period. A constant voltage is applied from the line during the first period. The gray-scale voltage is applied from the line during a second period, and the gate of the second transistor and the one terminal are short-circuited. In addition, an electric charge based on the difference between the gray-scale voltage and the gate voltage of the second transistor is accumulated in the capacitor element, and a sweep voltage is applied during the third period, so that the ON time of the second transistor is controlled.
摘要翻译：显示元件的驱动电路包括具有第一晶体管和保持电路的电流源电路，所述保持电路用于在第一周期期间保持与要提供给显示元件的恒定电流相对应的电位的第一晶体管的栅极电压，以及控制电路，包括与所述电流源电路串联连接并并联连接到所述显示元件的第二晶体管和所述电容器元件，所述电容器元件的一个端子连接到所述第二晶体管的栅极，并且所述另一端子连接到线路，以及通过在第三周期期间控制所述第二晶体管来控制所述显示元件的发光时间。在第一周期期间从线路施加恒定电压。在第二周期期间，从线路施加灰度电压，并且第二晶体管的栅极和一个端子短路。此外，基于第二晶体管的灰度电压和栅极电压之间的差异的电荷累积在电容器元件中，并且在第三周期期间施加扫描电压，使得第二时间的导通时间晶体管被控制。

27. 发明授权

US08445902B2 Thin film transistor and method of manufacturing the same 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US08445902B2
公开(公告)日：2013-05-21
申请号：US12990408
申请日：2009-04-28
申请人： Ayumu Sato , Ryo Hayashi , Hisato Yabuta , Masafumi Sano
发明人： Ayumu Sato , Ryo Hayashi , Hisato Yabuta , Masafumi Sano
IPC分类号： H01L29/10 , H01L29/12
CPC分类号： H01L29/7869 , H01L29/78621
摘要： Provided are a coplanar structure thin film transistor that allows a threshold voltage to change only a little under electric stress, and a method of manufacturing the same. The thin film transistor includes on a substrate at least: a gate electrode; a gate insulating layer; an oxide semiconductor layer including a source electrode, a drain electrode, and a channel region; a channel protection layer; and an interlayer insulating layer. The channel protection layer includes one or more layers, the layer in contact with the oxide semiconductor layer among the one or more layers being made of an insulating material containing oxygen, ends of the channel protection layer are thinner than a central part of the channel protection layer, the interlayer insulating layer contains hydrogen, and regions of the oxide semiconductor layer that are in direct contact with the interlayer insulating layer form the source electrode and the drain electrode.
摘要翻译：提供一种共面结构薄膜晶体管，其制造方法允许阈值电压在电应力下变化很小。薄膜晶体管至少在基板上包括：栅电极; 栅极绝缘层; 包括源电极，漏电极和沟道区的氧化物半导体层; 通道保护层; 和层间绝缘层。沟道保护层包括一层或多层，一层或多层中与氧化物半导体层接触的层由含氧的绝缘材料制成，沟道保护层的端部比通道保护层的中心部分薄层间绝缘层含有氢，与层间绝缘层直接接触的氧化物半导体层的区域形成源电极和漏电极。

28. 发明授权

US08084331B2 Method of treating semiconductor element 有权
标题翻译：半导体元件的处理方法
公开(公告)号：US08084331B2
公开(公告)日：2011-12-27
申请号：US12865032
申请日：2009-03-02
申请人： Masato Ofuji , Katsumi Abe , Hisae Shimizu , Ryo Hayashi , Masafumi Sano , Hideya Kumomi , Yasuyoshi Takai , Takehiko Kawasaki , Norio Kaneko
发明人： Masato Ofuji , Katsumi Abe , Hisae Shimizu , Ryo Hayashi , Masafumi Sano , Hideya Kumomi , Yasuyoshi Takai , Takehiko Kawasaki , Norio Kaneko
IPC分类号： H01L21/331
CPC分类号： H01L29/7869 , H01L29/66969 , H01L29/78633
摘要： In a method of treating a semiconductor element which at least includes a semiconductor, a threshold voltage of the semiconductor element is changed by irradiating the semiconductor with light with a wavelength longer than an absorption edge wavelength of the semiconductor. The areal density of in-gap states in the semiconductor is 1013 cm−2eV−1 or less. The band gap may be 2 eV or greater. The semiconductor may include at least one selected from the group consisting of In, Ga, Zn and Sn. The semiconductor may be one selected from the group consisting of amorphous In—Ga—Zn—O (IGZO), amorphous In—Zn—O (IZO) and amorphous Zn—Sn—O (ZTO). The light irradiation may induce the threshold voltage shift in the semiconductor element, the shift being of the opposite sign to the threshold voltage shift caused by manufacturing process history, time-dependent change, electrical stress or thermal stress.
摘要翻译：在处理至少包括半导体的半导体元件的方法中，通过用比半导体的吸收边缘波长更长的光照射半导体来改变半导体元件的阈值电压。半导体中间隙状态的面密度为1013cm-2eV-1或更小。带隙可以是2eV或更大。半导体可以包括选自In，Ga，Zn和Sn中的至少一种。半导体可以是选自由无定形In-Ga-Zn-O（IGZO），非晶In-Zn-O（IZO）和无定形Zn-Sn-O（ZTO）组成的组中的一种。光照射可以引起半导体元件中的阈值电压偏移，该偏移与由制造工艺历史，时间依赖变化，电应力或热应力引起的阈值电压偏移相反。

29. 发明申请

US20110042670A1 THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20110042670A1
公开(公告)日：2011-02-24
申请号：US12990408
申请日：2009-04-28
申请人： Ayumu Sato , Ryo Hayashi , Hisato Yabuta , Masafumi Sano
发明人： Ayumu Sato , Ryo Hayashi , Hisato Yabuta , Masafumi Sano
IPC分类号： H01L29/786 , H01L21/44
CPC分类号： H01L29/7869 , H01L29/78621
摘要： Provided are a coplanar structure thin film transistor that allows a threshold voltage to change only a little under electric stress, and a method of manufacturing the same. The thin film transistor includes on a substrate at least: a gate electrode; a gate insulating layer; an oxide semiconductor layer including a source electrode, a drain electrode, and a channel region; a channel protection layer; and an interlayer insulating layer. The channel protection layer includes one or more layers, the layer in contact with the oxide semiconductor layer among the one or more layers being made of an insulating material containing oxygen, ends of the channel protection layer are thinner than a central part of the channel protection layer, the interlayer insulating layer contains hydrogen, and regions of the oxide semiconductor layer that are in direct contact with the interlayer insulating layer form the source electrode and the drain electrode.
摘要翻译：提供一种共面结构薄膜晶体管，其制造方法允许阈值电压在电应力下变化很小。薄膜晶体管至少在基板上包括：栅电极; 栅极绝缘层; 包括源电极，漏电极和沟道区的氧化物半导体层; 通道保护层; 和层间绝缘层。沟道保护层包括一层或多层，一层或多层中与氧化物半导体层接触的层由含氧的绝缘材料制成，沟道保护层的端部比通道保护层的中心部分薄层间绝缘层含有氢，与层间绝缘层直接接触的氧化物半导体层的区域形成源电极和漏电极。

30. 发明授权

US07855379B2 Electron device using oxide semiconductor and method of manufacturing the same 有权
标题翻译：使用氧化物半导体的电子器件及其制造方法
公开(公告)号：US07855379B2
公开(公告)日：2010-12-21
申请号：US12123103
申请日：2008-05-19
申请人： Ryo Hayashi , Masafumi Sano
发明人： Ryo Hayashi , Masafumi Sano
IPC分类号： H01L29/10
CPC分类号： H01L29/7869 , H01L27/1225
摘要： In an electron device in which plural thin film transistors each having at least a source electrode, a drain electrode, a semiconductor region including a channel, a gate insulation film and a gate electrode are provided on a substrate, a device separation region provided between the plural thin film transistors and the semiconductor region are constituted by a same metal oxide layer, and resistance of the semiconductor region is formed to be lower than resistance of the device separation region.
摘要翻译：在基板上设置有至少具有源电极，漏电极，包括沟道的半导体区域，栅极绝缘膜和栅极电极的多个薄膜晶体管的电子器件，设置在基板之间的器件分离区域多个薄膜晶体管和半导体区域由相同的金属氧化物层构成，半导体区域的电阻形成为低于器件分离区域的电阻。

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