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21. 发明授权

US5428626A Timing analyzer for embedded testing 失效
标题翻译：嵌入式测试定时分析仪
公开(公告)号：US5428626A
公开(公告)日：1995-06-27
申请号：US138856
申请日：1993-10-18
申请人： Arnold M. Frisch , Thomas A. Almy
发明人： Arnold M. Frisch , Thomas A. Almy
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/319 , G01R31/3193 , G06F11/00
CPC分类号： G01R31/31937 , G01R31/318513 , G01R31/31858 , G01R31/31908 , G01R31/3191 , G01R31/31922
摘要： A timing analyzer for embedded testing of printed circuit boards, integrated circuits or multi-chip modules is in the form of an integrated circuit that may be included as part of the printed circuit board, integrated circuit or multi-chip module being tested. Each channel of a data path to be tested has a timing analyzer circuit that may be coupled into the path when enabled for testing. The timing analyzer circuit has instruction memories that are loaded with time event commands via a suitable program bus, such as a boundary scan interface. Each event command has a clock portion, an interpolation portion and a drive output portion. A counter counts down the clock portion using a system clock from the board/circuit/module to produce a terminate pulse. The terminate pulse is delayed by an increment less than one period of the system clock by a delay interpolator, the amount of delay being determined by the interpolation portion, to generate a trigger signal. The trigger signal clocks a capture register to acquire the logic level at a selected one of the pins, and optionally causes a selected output to be driven according to the drive output portion. A shared delay calibration circuit uses a charge-pumped phase locked loop to generate a precision supply voltage for the delay elements in the delay interpolator, the delay for each delay element being a function of the applied supply voltage.
摘要翻译：用于印刷电路板，集成电路或多芯片模块的嵌入式测试的定时分析仪是集成电路的形式，其可以作为被测试的印刷电路板，集成电路或多芯片模块的一部分被包括。要测试的数据路径的每个通道具有定时分析器电路，其可以在启用测试时耦合到路径中。定时分析器电路具有通过合适的程序总线（如边界扫描接口）加载时间事件命令的指令存储器。每个事件命令具有时钟部分，内插部分和驱动器输出部分。计数器使用来自电路板/电路/模块的系统时钟对时钟部分进行计数以产生终止脉冲。终止脉冲通过延迟内插器延迟小于系统时钟的一个周期的延迟，延迟量由内插部分确定，以产生触发信号。触发信号对捕获寄存器进行时钟采集以在所选择的一个引脚处获取逻辑电平，并且可选地使所选输出根据驱动器输出部分被驱动。共享延迟校准电路使用电荷泵浦锁相环来为延迟内插器中的延迟元件产生精确的电源电压，每个延迟元件的延迟是所施加的电源电压的函数。

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