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21. 发明授权

US5764165A Rotated counter bit pulse width modulated digital to analog converter 失效
标题翻译：旋转计数器位脉宽调制数模转换器
公开(公告)号：US5764165A
公开(公告)日：1998-06-09
申请号：US642754
申请日：1996-05-03
申请人： Bruce D. Buch
发明人： Bruce D. Buch
IPC分类号： H03M5/08
CPC分类号： H03M5/08
摘要： A pulse width modulated, digital-to-analog converter (PWM DAC) that includes a pulse generator for generating width modulated pulses in accordance with a digital control value is set forth. The generator includes a clock for generating a clocking signal, a counter responsive to the clocking signal for generating repeating sequences of N-bit counts, each sequence representing a count interval. The PWM DAC further includes a bit rotator for receiving the sequences of N-bit counts and for rotating the bit position of at least a most significant one of N-bits. A latch holds a digital control value, whereby a comparator compares the digital control value with each one of the rotated bit counts to put out the width modulated pulses during the count interval. The rotated bit counts increases the frequency of the comparator, in a substantially linear manner, such that subsequent filtering can be accomplished with minimum time requirements.
摘要翻译：阐述了脉冲宽度调制的数模转换器（PWM DAC），其包括用于根据数字控制值产生宽度调制脉冲的脉冲发生器。发生器包括用于产生时钟信号的时钟，响应于时钟信号的计数器，用于产生重复的N位计数序列，每个序列表示计数间隔。 PWM DAC还包括用于接收N位计数序列并用于旋转至少最高有效N位的位位置的位旋转器。锁存器保持数字控制值，由此比较器将数字控制值与旋转位计数中的每一个进行比较，以在计数间隔期间输出宽度调制脉冲。旋转的位计数以基本线性的方式增加比较器的频率，使得可以以最小的时间要求来实现后续的滤波。

22. 发明授权

US5239634A Memory controller for enqueuing/dequeuing process 失效
标题翻译：用于排队/排队过程的内存控制器
公开(公告)号：US5239634A
公开(公告)日：1993-08-24
申请号：US410600
申请日：1989-09-21
申请人： Bruce D. Buch , Cecil D. MacGregor
发明人： Bruce D. Buch , Cecil D. MacGregor
IPC分类号： G06F9/46 , G06F12/02 , G06F13/16
CPC分类号： G06F9/52 , G06F12/0284 , G06F13/1642
摘要： A memory controller manipulated enqueuing and dequeuing process for singly linked queues in a memory system in response to single exclusive-access write and read commands from any CPU in the associated data processing system.
摘要翻译：存储器控制器响应于来自相关联的数据处理系统中的任何CPU的单独的独占访问写入和读取命令，对存储器系统中的单链路队列进行排队和排队过程。

23. 发明授权

US06191906B1 Method for estimating sampling phase from synchronously demodulated samples of sinusoidal waveforms 有权
标题翻译：用于从同步解调的正弦波形样本估计采样相位的方法
公开(公告)号：US06191906B1
公开(公告)日：2001-02-20
申请号：US09306233
申请日：1999-05-06
申请人： Bruce D. Buch
发明人： Bruce D. Buch
IPC分类号： G11B509
CPC分类号： G11B20/10055 , G11B5/012 , G11B5/09 , G11B20/1403 , G11B20/1426
摘要： A timing error extractor (166) determines the phase angle between an input signal and a sampling clock by computing arctan(v/u)=arctan(alog(log(v)−log(u)), where (v) and (u) are the respective quadrature amplitudes of the input signal and sampling clock. The log function values are stored in a first lookup table (180) that is time-shared by a switching function (182) to provide both log(v) and log(u) values. A storage element (184) holds the log(u) value while the switching function routes magnitude (v) to the first lookup table. The resulting log(v) value and the stored log(u) are combined in a subtraction function (186) that generates log(v)−log(u), which result addresses a second lookup table (188) that returns the addressed arctan(alog(log(v)−log(u)) value. This phase estimating approach is advantageous because it is gain insensitive, does not include a costly and time-consuming divide operation, and requires a relatively small lookup table.
摘要翻译：定时误差提取器（166）通过计算arctan（v / u）= arctan（alog（log（v）-log（u））来确定输入信号和采样时钟之间的相位角，其中（v）和（u ）是输入信号和采样时钟的相应正交幅度，对数函数值存储在由切换功能（182）共享的第一查找表（180）中，以提供log（v）和log（ u）值存储元素（184）保存log（u）值，而切换功能将幅度（v）路由到第一查找表，生成的log（v）值和存储的log（u）生成log（v）-log（u）的减法函数（186），其结果寻址返回寻址的arctan（alog（log（v）-log（u））值的第二查找表（188）方法是有利的，因为它是增益不敏感的，不包括昂贵且耗时的划分操作，并且需要相对较小的查找表。

24. 发明授权

US5712636A Pulse-width-modulated digital-to-analog converter with high gain and low gain modes 失效
标题翻译：具有高增益和低增益模式的脉宽调制数模转换器
公开(公告)号：US5712636A
公开(公告)日：1998-01-27
申请号：US677147
申请日：1996-07-09
申请人： Bruce D. Buch
发明人： Bruce D. Buch
IPC分类号： H03M1/82
CPC分类号： H03M1/825
摘要： A pulse-width-modulated digital-to-analog converter is responsive to a digital control value for switching between a high gain mode and a low gain mode. The converter includes a free-running rollover counter, a reference register and a comparator. Pulses from a comparator are split into two paths, one path including a switch, and fed into a plurality of resistive elements connected connected to a common output node. Depending on the state of the switch, the network's output value will either follow its input or be a fraction thereof, without change of duty cycle or output impedance. The output node may be connected to a capacitive element to form a low pass filter for generating an analog waveform.
摘要翻译：脉冲宽度调制的数模转换器响应用于在高增益模式和低增益模式之间切换的数字控制值。转换器包括一个自由运行的翻转计数器，一个参考寄存器和一个比较器。来自比较器的脉冲被分成两个路径，一个路径包括一个开关，并被馈送到连接到公共输出节点的多个电阻元件。根据交换机的状态，网络的输出值将跟随其输入或其一部分，而不改变占空比或输出阻抗。输出节点可以连接到电容元件以形成用于产生模拟波形的低通滤波器。

25. 发明授权

US5669002A Multi-processor resource locking mechanism with a lock register corresponding to each resource stored in common memory 失效
标题翻译：多处理器资源锁定机制，具有对应于存储在公共存储器中的每个资源的锁定寄存器
公开(公告)号：US5669002A
公开(公告)日：1997-09-16
申请号：US569555
申请日：1995-12-08
申请人： Bruce D. Buch
发明人： Bruce D. Buch
IPC分类号： G06F9/46 , G06F12/02 , G06F12/14 , G06F15/167
CPC分类号： G06F9/52
摘要： A method and apparatus to reduce bus usage and to increase resource locking protocol compatibility within a heterogeneous processing environment. Lock indicators are maintained in stores designated as lock registers and access to a resource is gained by any processor depending upon the status of a lock register associated with that resource. Access to a locked resource is barred to all but the locking processor, and only the processor which has set a lock can use or release that locked resource. A lock register controller controls the contents of the lock registers. A given processor P1-PN is identified by a unique ID vector G1-GN. These vectors are used to indicate both that a resource is locked and to indicate the identity of the locking processor. An unlocked resource is identified by a status vector (G.O slashed.). In a preferred embodiment, acquisition of exclusive access to an available resource is obtained with a simple read command; release of exclusive access is achieved with a simple write executed by the processor which has set the lock. By convention, processors will not access a resource requiring exclusive access until an inquiry of the associated lock register returns the G.O slashed. vector to the inquiring processor.
摘要翻译：一种在异构处理环境中减少总线使用并增加资源锁定协议兼容性的方法和装置。锁定指示器被保存在指定为锁定寄存器的存储器中，并且根据与该资源相关联的锁定寄存器的状态，任何处理器获得对资源的访问。除了锁定处理器之外，对锁定资源的访问被禁止，只有设置了锁定的处理器才能使用或释放锁定的资源。锁定寄存器控制器控制锁定寄存器的内容。给定处理器P1-PN由唯一的ID矢量G1-GN识别。这些向量用于指示资源被锁定并指示锁定处理器的标识。解锁资源由状态向量（G + 527）标识。在优选实施例中，通过简单的读取命令来获得对可用资源的独占访问; 通过已设置锁定的处理器执行的简单写入来实现专用访问的释放。按照惯例，处理器将不会访问需要独占访问的资源，直到相关锁定寄存器的查询将G + 527向量返回给查询处理器。

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