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21. 发明授权

US08590010B2 Retention based intrinsic fingerprint identification featuring a fuzzy algorithm and a dynamic key 有权
标题翻译：基于保留的内在指纹识别，具有模糊算法和动态密钥
公开(公告)号：US08590010B2
公开(公告)日：2013-11-19
申请号：US13302314
申请日：2011-11-22
申请人： Daniel J. Fainstein , Alberto Cestero , Subramanian S. Iyer , Toshiaki Kirihata , Norman W. Robson , Sami Rosenblatt
发明人： Daniel J. Fainstein , Alberto Cestero , Subramanian S. Iyer , Toshiaki Kirihata , Norman W. Robson , Sami Rosenblatt
IPC分类号： H03M13/05
CPC分类号： G06F21/73 , G06F21/44 , G06F2221/2103 , G09C1/00 , H04L9/3278 , H04L2209/127
摘要： A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.
摘要翻译：随机内在芯片ID生成采用保留失败签名。使用测试设置生成第1和第2个ID，第一个设置比第二个设置的限制要大于第二个设置，在包含第二个ID位串的第一个ID位字符串中创建更多的故障。保留暂停时间控制由BIST引擎调整的保留失败次数，其中失败号码满足预定的失败目标。验证确认第一ID是否包含第二ID位字符串，该ID是用于认证的ID。认证由具有中间条件的第三ID启用，使得第一ID包括第三ID位串，第三ID包括第二ID位串。中间条件包括用于消除第1和第2 ID边界附近的位不稳定性问题的保护带。在每次ID读取操作中改变中间条件，导致更安全的识别。

22. 发明申请

US20130168673A1 Intra Die Variation Monitor Using Through-Silicon Via 失效
标题翻译：使用硅片的内部晶片变化监视器
公开(公告)号：US20130168673A1
公开(公告)日：2013-07-04
申请号：US13342226
申请日：2012-01-03
申请人： Xiaojun Yu , Anda C. Mocuta , Toshiaki Kirihata
发明人： Xiaojun Yu , Anda C. Mocuta , Toshiaki Kirihata
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/34 , H01L23/481 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.
摘要翻译：一种设备，包括通过硅通孔（TSV）连接IDVMON监视器，以使监视器能够连接到位于晶片背面的探针焊盘。因为晶片的背面具有比前侧大得多的空间，所以可以容纳用于IDVMON的探针垫，而不牺牲硅面积。

23. 发明申请

US20130133031A1 Retention Based Intrinsic Fingerprint Identification Featuring A Fuzzy Algorithm and a Dynamic Key 有权
标题翻译：基于保留的内在指纹识别具有模糊算法和动态密钥
公开(公告)号：US20130133031A1
公开(公告)日：2013-05-23
申请号：US13302314
申请日：2011-11-22
申请人： Daniel J. Fainstein , Alberto Cestero , Subramanian S. Iyer , Toshiaki Kirihata , Norman W. Robson , Sami Rosenblatt
发明人： Daniel J. Fainstein , Alberto Cestero , Subramanian S. Iyer , Toshiaki Kirihata , Norman W. Robson , Sami Rosenblatt
IPC分类号： G06F21/00
CPC分类号： G06F21/73 , G06F21/44 , G06F2221/2103 , G09C1/00 , H04L9/3278 , H04L2209/127
摘要： A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.
摘要翻译：随机内在芯片ID生成采用保留失败签名。使用测试设置生成第1和第2个ID，第一个设置比第二个设置的限制要大于第二个设置，在包含第二个ID位串的第一个ID位字符串中创建更多的故障。保留暂停时间控制由BIST引擎调整的保留失败次数，其中失败号码满足预定的失败目标。验证确认第一ID是否包含第二ID位字符串，该ID是用于认证的ID。认证由具有中间条件的第三ID启用，使得第一ID包括第三ID位串，第三ID包括第二ID位串。中间条件包括用于消除第1和第2 ID边界附近的位不稳定性问题的保护带。在每次ID读取操作中改变中间条件，导致更安全的识别。

24. 发明授权

US07774660B2 Flexible row redundancy system 失效
标题翻译：灵活的行冗余系统
公开(公告)号：US07774660B2
公开(公告)日：2010-08-10
申请号：US12131307
申请日：2008-06-02
申请人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
发明人： Louis L. Hsu , Gregory J. Fredeman , Rajiv V. Joshi , Toshiaki Kirihata
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.
摘要翻译：提供了一种用于替换具有多个存储体的存储器阵列的有缺陷的字线的行冗余系统。行冗余系统包括存储与存储器阵列的故障字线相对应的至少一个故障地址的远程熔丝架; 用于存储对应于所述存储器阵列的至少一个组的行熔丝信息的行熔丝阵列; 以及复制逻辑模块，用于将存储在所述远程保险丝盒中的至少一个故障地址复制到所述行保险丝阵列中; 其中所述复制逻辑模块被编程为根据可选择的修复字段大小将所述至少一个故障地址复制到对应于预定数量的存储体的行熔丝阵列中的行熔丝信息。

25. 发明申请

US20090103390A1 Three Dimensional Twisted Bitline Architecture for Multi-port Memory 失效
标题翻译：用于多端口存储器的三维扭转位线架构
公开(公告)号：US20090103390A1
公开(公告)日：2009-04-23
申请号：US11875173
申请日：2007-10-19
申请人： Hoki Kim , Toshiaki Kirihata
发明人： Hoki Kim , Toshiaki Kirihata
IPC分类号： G11C8/00
CPC分类号： G11C8/16 , G11C7/02 , G11C7/1075 , G11C7/18 , G11C11/412
摘要： Embodiments of the present invention provide a memory array of dual part cells and design structure thereof. The memory array has a pair of twisted write bit lines and a pair of twisted read bit lines for each column. The twist is made by alternating the vertical position of each bit line pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.
摘要翻译：本发明的实施例提供了双重部分单元的存储器阵列及其设计结构。存储器阵列具有一对扭曲的写位线和用于每列的一对扭转的读位线。通过在列的每个部分中交替每个位线对的垂直位置来进行扭转，从而产生共模鼻子并且减小差模噪声。

26. 发明授权

US07194670B2 Command multiplier for built-in-self-test 有权
标题翻译：内置自检命令乘数
公开(公告)号：US07194670B2
公开(公告)日：2007-03-20
申请号：US10708184
申请日：2004-02-13
申请人： Jonathan R. Fales , Gregory J. Fredeman , Kevin W. Gorman , Mark D. Jacunski , Toshiaki Kirihata , Alan D. Norris , Paul C. Parries , Matthew R. Wordeman
发明人： Jonathan R. Fales , Gregory J. Fredeman , Kevin W. Gorman , Mark D. Jacunski , Toshiaki Kirihata , Alan D. Norris , Paul C. Parries , Matthew R. Wordeman
IPC分类号： G01R31/28
CPC分类号： G11C29/16 , G11C29/12015 , G11C29/14 , G11C2029/0401
摘要： Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.
摘要翻译：公开了用于高速嵌入式存储器阵列的内置自检（BIST）的灵活的命令乘法方案，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。独立的BIST逻辑控制器以较低的频率工作，并与使用低速BIST指令种子集的命令乘法器进行通信。命令乘法器使用偏移或指令寄存器来驱动逻辑单元或ALU以产生“n”组CAD信息，然后以比BIST操作速度快n倍的速度将时间复用到嵌入式存储器。

27. 发明申请

US20050157577A1 Concurrent refresh mode with distributed row address counters in an embedded DRAM 有权
公开(公告)号：US20050157577A1
公开(公告)日：2005-07-21
申请号：US10757846
申请日：2004-01-15
申请人： John Barth , Toshiaki Kirihata , Paul Parries
发明人： John Barth , Toshiaki Kirihata , Paul Parries
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/40618 , G11C11/406 , G11C2207/104
摘要： A concurrent refresh mode is realized by allowing a memory array to be refreshed by way of a refresh bank select signal, while concurrently enabling a memory access operation in another array. The refresh address management is greatly simplified by the insertion of row address counter integrated within each array. In the preferred embodiment, any combination of a plurality of the memory arrays is refreshed simultaneously while enabling a memory access operation. This concurrent mode also supports a multi-bank operation.

28. 发明授权

US06845033B2 Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technology 失效
标题翻译：用于沟槽技术的双晶体管和双电容器存储单元的结构和片上系统集成
公开(公告)号：US06845033B2
公开(公告)日：2005-01-18
申请号：US10248954
申请日：2003-03-05
申请人： Toshiaki Kirihata , John W. Golz
发明人： Toshiaki Kirihata , John W. Golz
IPC分类号： H01L27/108 , G11C11/24 , G11C11/401 , G11C11/404 , H01L21/8242
CPC分类号： G11C11/404 , H01L27/108 , H01L27/10829
摘要： A two-port dynamic random access memory (DRAM) cell consisting of two transistors and two trench capacitors (2T and 2C DRAM cell) connecting two one transistor and one capacitor DRAM cell (1T DRAM cell) is described. The mask data and cross-section of the 2T 2C DRAM and 1T DRAM cells are fully compatible to each other except for the diffusion connection that couples two storage nodes of the two 1T DRAM cells. This allows a one-port memory cell with 1T and 1C DRAM cell and a two-port memory cell with 2T and 2C DRAM cell to be fully integrated, forming a true system-on chip architecture. Alternatively, by halving the capacitor, the random access write cycle time is further reduced, while still maintaining the data retention time. The deep trench process time is also reduced by reducing by one-half the trench depth.
摘要翻译：描述了连接两个晶体管和一个电容器DRAM单元（1T DRAM单元）的两个晶体管和两个沟槽电容器（2T和2C DRAM单元）组成的双端口动态随机存取存储器（DRAM）单元。除了连接两个1T DRAM单元的两个存储节点的扩散连接之外，2T 2C DRAM和1T DRAM单元的掩模数据和横截面彼此完全兼容。这允许具有1T和1C DRAM单元的单端口存储器单元和具有2T和2C DRAM单元的双端口存储器单元被完全集成，形成真正的片上系统体系结构。或者，通过将电容器减半，随机存取写周期时间进一步降低，同时仍然保持数据保留时间。深沟槽加工时间也减少了沟槽深度的一半。

29. 发明授权

US06690198B2 Repeater with reduced power consumption 有权
标题翻译：中继器具有降低的功耗
公开(公告)号：US06690198B2
公开(公告)日：2004-02-10
申请号：US10114195
申请日：2002-04-02
申请人： Gerhard Mueller , Toshiaki Kirihata
发明人： Gerhard Mueller , Toshiaki Kirihata
IPC分类号： H03K190175
CPC分类号： H03K19/01721 , G11C7/1048 , G11C7/1069 , G11C11/4096 , H03K19/0013
摘要： A repeater circuit having improved switching speed and reduced power consumption is described. The repeater circuit is configured to receive an input signal from a first segment of a signal line and pass the signal to a second segment of the signal line in response to an active control signal.
摘要翻译：描述了具有改进的开关速度和降低的功耗的中继器电路。中继器电路被配置为从信号线的第一段接收输入信号，并且响应于主动控制信号将信号传递到信号线的第二段。

30. 发明授权

US06587388B2 Method and apparatus for reducing write operation time in dynamic random access memories 失效
公开(公告)号：US06587388B2
公开(公告)日：2003-07-01
申请号：US09844837
申请日：2001-04-27
申请人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh
发明人： Toshiaki Kirihata , Sang Hoo Dhong , Hwa-Joon Oh
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C11/4076
摘要： A method for preparing a dynamic random access memory (DRAM) cell for a write operation with a preset condition is disclosed. In an exemplary embodiment, the method includes creating a preset voltage level within the cell prior to a delayed write back in a destructive read architecture, which preset voltage level has a value between a logic 0 voltage level and a logic 1 voltage level. The logic 0 voltage level corresponds to a first cell voltage value when the cell has a 0 bit stored therein, and the logic 1 voltage level corresponds to a second cell voltage value when the cell has a 1 bit stored therein. Prior to the creation of the preset voltage level within the cell, the cell has an initial voltage value corresponding to either the logic 0 voltage level or the logic 1 voltage level.

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