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21. 发明授权

US08324041B2 Complementary stress liner to improve DGO/AVT devices and poly and diffusion resistors 有权
标题翻译：互补应力衬垫，用于改善DGO / AVT器件和聚和扩散电阻器
公开(公告)号：US08324041B2
公开(公告)日：2012-12-04
申请号：US13023794
申请日：2011-02-09
申请人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
发明人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L21/8238
CPC分类号： H01L28/20 , H01L29/78 , H01L29/7843
摘要： Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.
摘要翻译：通过使用互补应力衬垫，在长沟道半导体器件和电阻器中电子迁移率和空穴迁移率得到改善。实施例包括在衬底上形成长沟道半导体器件，并在半导体器件上形成互补应力衬垫。实施例包括在衬底上形成电阻器，并通过在电阻器上形成互补应力衬垫来调节电阻器的电阻。使用压缩应力衬垫来改善n型器件中的电子迁移率，并且使用拉伸应力衬垫来改善p型器件中的空穴迁移率。

22. 发明申请

US20120292637A1 Dual Cavity Etch for Embedded Stressor Regions 审中-公开
标题翻译：嵌入式应力区域的双腔蚀刻
公开(公告)号：US20120292637A1
公开(公告)日：2012-11-22
申请号：US13109134
申请日：2011-05-17
申请人： Sven Beyer , Peter Baars , Jan Hoentschel , Thilo Scheiper
发明人： Sven Beyer , Peter Baars , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238 , H01L21/20
CPC分类号： H01L21/823807 , H01L21/02532 , H01L21/0262 , H01L21/823814 , H01L21/84 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Generally, the present disclosure is directed to methods for forming embedded stressor regions in semiconductor devices such as transistor elements and the like. One illustrative method disclosed herein includes forming a first material in first cavities formed in a first active area adjacent to a first channel region of a semiconductor device, wherein the first material induces a first stress in the first channel region. The method also includes, among other things, forming a second material in second cavities formed in a second active area adjacent to a second channel region of the semiconductor device, wherein the second material induces a second stress in the second channel region that is of an opposite type of the first stress in the first channel region, and wherein the first and second cavities are formed during a common etch process.
摘要翻译：通常，本公开涉及在诸如晶体管元件等的半导体器件中形成嵌入的应力源区域的方法。本文公开的一种说明性方法包括在与半导体器件的第一沟道区相邻的第一有源区中形成的第一空腔中形成第一材料，其中第一材料在第一沟道区域中引起第一应力。该方法还包括在形成在与半导体器件的第二沟道区相邻的第二有源区中的第二腔中形成第二材料，其中第二材料在第二沟道区域中引起第二应力在第一通道区域中相反类型的第一应力，并且其中第一和第二空腔在公共蚀刻工艺期间形成。

23. 发明申请

US20120280289A1 Method of Increasing the Germanium Concentration in a Silicon-Germanium Layer and Semiconductor Device Comprising Same 有权
标题翻译：增加硅锗层中的锗浓度的方法和包括其的半导体器件
公开(公告)号：US20120280289A1
公开(公告)日：2012-11-08
申请号：US13101659
申请日：2011-05-05
申请人： Stefan Flachowsky , Thilo Scheiper , Peter Javorka , Jan Hoentschel
发明人： Stefan Flachowsky , Thilo Scheiper , Peter Javorka , Jan Hoentschel
IPC分类号： H01L29/772 , H01L21/20
CPC分类号： H01L21/02587 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/823807 , H01L21/84 , H01L29/1054 , H01L29/161 , H01L29/66431 , H01L29/66651 , H01L29/7781 , H01L29/7833
摘要： Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming layer of silicon germanium on a P-active region of a semiconducting substrate wherein the layer of silicon germanium has a first concentration of germanium, and performing an oxidation process on the layer of silicon germanium to increase a concentration of germanium in at least a portion of the layer of silicon germanium to a second concentration that is greater than the first concentration of germanium.
摘要翻译：本文公开了形成半导体器件的方法。在一个示例中，该方法包括在半导体衬底的P活性区上形成硅锗层，其中硅锗层具有锗的第一浓度，并且在硅锗层上进行氧化处理以增加浓度在硅锗层的至少一部分中的锗至大于锗的第一浓度的第二浓度。

24. 发明申请

US20120196422A1 Stress Memorization Technique Using Gate Encapsulation 审中-公开
标题翻译：使用门封装的应力记忆技术
公开(公告)号：US20120196422A1
公开(公告)日：2012-08-02
申请号：US13015329
申请日：2011-01-27
申请人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
发明人： Stefan Flachowsky , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L21/336 , H01L21/4763
CPC分类号： H01L29/7845 , H01L21/28518 , H01L21/76829 , H01L21/76837 , H01L29/66545 , H01L29/6656 , H01L29/7843 , H01L29/7847
摘要： Generally, the subject matter disclosed herein relates to sophisticated semiconductor devices and methods for forming the same, wherein a stress memorization technique is used to enhance the performance of MOS transistor elements. One illustrative embodiment includes a method for forming a gate electrode above a channel region of a semiconductor device, wherein the channel region is formed in an active region of a semiconductor substrate. The method further includes forming a dielectric encapsulating layer in direct contact with the gate electrode, and performing a heat treatment process to induce a residual stress in the channel region.
摘要翻译：通常，本文公开的主题涉及复杂的半导体器件及其形成方法，其中使用应力存储技术来增强MOS晶体管元件的性能。一个说明性实施例包括在半导体器件的沟道区上方形成栅电极的方法，其中沟道区形成在半导体衬底的有源区中。该方法还包括形成与栅电极直接接触的电介质封装层，并进行热处理工艺以在沟道区域中引起残余应力。

25. 发明申请

US20120171830A1 ASYMMETRIC TRANSISTOR DEVICES FORMED BY ASYMMETRIC SPACERS AND TILTED IMPLANTATION 有权
标题翻译：由不对称间距和倾斜植入形成的不对称晶体管器件
公开(公告)号：US20120171830A1
公开(公告)日：2012-07-05
申请号：US13417651
申请日：2012-03-12
申请人： Jan Hoentschel , Uwe Griebenow , Maciej Wiatr
发明人： Jan Hoentschel , Uwe Griebenow , Maciej Wiatr
IPC分类号： H01L21/336
CPC分类号： H01L21/823468 , H01L21/823425 , H01L21/823864
摘要： An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.
摘要翻译：公开了一种非对称晶体管结构，其中非对称延伸区域和/或卤素区域可与非对称间隔物结构组合，其可用于进一步调整不对称晶体管的整体掺杂物分布。

26. 发明申请

US20120161203A1 Strain Enhancement in Transistors Comprising an Embedded Strain-Inducing Semiconductor Material by Alloy Species Condensation 审中-公开
标题翻译：包含嵌入式应变诱导半导体材料的晶体管中的应变增强合金种类冷凝
公开(公告)号：US20120161203A1
公开(公告)日：2012-06-28
申请号：US13196318
申请日：2011-08-02
申请人： Stefan Flachowsky , Stephan-Detlef Kronholz , Jan Hoentschel , Thilo Scheiper
发明人： Stefan Flachowsky , Stephan-Detlef Kronholz , Jan Hoentschel , Thilo Scheiper
IPC分类号： H01L21/336 , H01L21/225 , H01L29/78 , B82Y99/00 , B82Y40/00
CPC分类号： H01L29/165 , H01L21/18 , H01L29/161 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： In transistors requiring a high compressive strain, the germanium contents may be increased by applying a germanium condensation technique. In some illustrative embodiments, an oxidation process is performed in the presence of a silicon/germanium material obtained on the basis of selective epitaxial growth techniques, thereby increasingly oxidizing the silicon species, while driving the germanium into the lower lying areas of the active region, which finally results in an increased germanium concentration.
摘要翻译：在需要高压缩应变的晶体管中，可以通过应用锗冷凝技术来增加锗含量。在一些说明性实施例中，在基于选择性外延生长技术获得的硅/锗材料的存在下进行氧化工艺，从而在将锗驱动到有源区的下部区域的同时越来越多地氧化硅种，这最终导致锗浓度增加。

27. 发明授权

US08183101B2 Multiple gate transistor having fins with a length defined by the gate electrode 有权
标题翻译：多栅极晶体管具有由栅电极限定的长度的散热片
公开(公告)号：US08183101B2
公开(公告)日：2012-05-22
申请号：US12620265
申请日：2009-11-17
申请人： Robert Mulfinger , Andy Wei , Jan Hoentschel , Andrew Waite
发明人： Robert Mulfinger , Andy Wei , Jan Hoentschel , Andrew Waite
IPC分类号： H01L29/78
CPC分类号： H01L29/66795 , H01L29/785
摘要： The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process.
摘要翻译：多栅极晶体管的漏极和源极区可以通过使用用于形成漏极和源极掺杂物分布的占位符结构而形成，而不需要外延生长工艺，随后掩蔽漏极和源极区域并去除占位符结构以露出沟道晶体管的面积。此后，可以对相应的翅片进行构图，并且可以形成栅电极结构。因此，由于避免了外延生长过程，可以实现缩短的循环时间。

28. 发明申请

US20110186915A1 REPLACEMENT GATE APPROACH BASED ON A REVERSE OFFSET SPACER APPLIED PRIOR TO WORK FUNCTION METAL DEPOSITION 有权
标题翻译：基于在工作功能金属沉积前应用的反向偏置孔的替代门控方法
公开(公告)号：US20110186915A1
公开(公告)日：2011-08-04
申请号：US12914570
申请日：2010-10-28
申请人： Thilo Scheiper , Sven Beyer , Uwe Griebenow , Jan Hoentschel
发明人： Thilo Scheiper , Sven Beyer , Uwe Griebenow , Jan Hoentschel
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/28105 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/66553 , H01L29/6659
摘要： In a replacement gate approach, a spacer may be formed in the gate opening after the removal of the placeholder material, thereby providing a superior cross-sectional shape upon forming any electrode metals in the gate opening. Moreover, the spacer may be used for reducing the gate length, while not requiring more complex gate patterning strategies.
摘要翻译：在替代门方法中，在移除占位符材料之后，可以在闸门开口中形成间隔件，从而在门开口中形成任何电极金属时提供优异的横截面形状。此外，间隔物可以用于减小栅极长度，而不需要更复杂的栅极图案化策略。

29. 发明授权

US07977225B2 Reducing implant degradation in tilted implantations by shifting implantation masks 有权
标题翻译：通过移植植入掩模减少倾斜植入中的植入物退化
公开(公告)号：US07977225B2
公开(公告)日：2011-07-12
申请号：US12417978
申请日：2009-04-03
申请人： Andre Poock , Jan Hoentschel
发明人： Andre Poock , Jan Hoentschel
IPC分类号： H01L21/425
CPC分类号： H01L21/823814 , H01L21/823807 , Y10S438/942 , Y10S438/944
摘要： In extremely scaled semiconductor devices, an asymmetric transistor configuration may be established on the basis of tilted implantation processes with increased resist height and/or tilt angles during tilted implantation processes by providing an asymmetric mask arrangement for masked transistor elements. For this purpose, the implantation mask may be shifted by an appropriate amount so as to enhance the overall blocking effect for the masked transistors while reducing any shadowing effect of the implantation masks for the non-masked transistors. The shift of the implantation masks may be accomplished by performing the automatic alignment procedure on the basis of “shifted” target values or by providing asymmetrically arranged photolithography masks.
摘要翻译：在非常规模的半导体器件中，可以通过提供用于被掩模的晶体管元件的不对称掩模布置，在倾斜注入工艺期间，在倾斜注入工艺的基础上，增加抗蚀剂高度和/或倾斜角度来建立非对称晶体管配置。为此，可以将注入掩模移动适当的量，以便增强掩模晶体管的总体阻塞效应，同时减少非掩蔽晶体管的注入掩模的任何阴影效应。注入掩模的移位可以通过基于“移位的”目标值执行自动对准过程或通过提供不对称布置的光刻掩模来实现。

30. 发明申请

US20110127616A1 WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS FOR DEVICES OF DIFFERENT THRESHOLD VOLTAGE 有权
标题翻译：用于不同阈值电压器件的高K栅极堆栈中的工作功能调整
公开(公告)号：US20110127616A1
公开(公告)日：2011-06-02
申请号：US12905501
申请日：2010-10-15
申请人： Jan Hoentschel , Sven Beyer , Thilo Scheiper
发明人： Jan Hoentschel , Sven Beyer , Thilo Scheiper
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/28176 , H01L21/823857 , H01L29/517
摘要： In sophisticated semiconductor devices, different threshold voltage levels for transistors may be set in an early manufacturing stage, i.e., prior to patterning the gate electrode structures, by using multiple diffusion processes and/or gate dielectric materials. In this manner, substantially the same gate layer stacks, i.e., the same electrode materials and the same dielectric cap materials, may be used, thereby providing superior patterning uniformity when applying sophisticated etch strategies.
摘要翻译：在复杂的半导体器件中，可以在早期制造阶段，即在通过使用多个扩散工艺和/或栅极电介质材料图案化栅极电极结构之前，将晶体管的不同阈值电压电平设置。以这种方式，可以使用基本相同的栅极层堆叠，即相同的电极材料和相同的电介质盖材料，从而在应用复杂的蚀刻策略时提供优异的图案均匀性。

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