专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US5834829A Energy relieving crack stop 失效
标题翻译：能量缓解裂缝停止
公开(公告)号：US5834829A
公开(公告)日：1998-11-10
申请号：US706586
申请日：1996-09-05
申请人： Bettina A. Dinkel , Pei-Ing Lee , Ernest N. Levine
发明人： Bettina A. Dinkel , Pei-Ing Lee , Ernest N. Levine
IPC分类号： H01L21/301 , H01L21/3205 , H01L21/768 , H01L21/78 , H01L23/52 , H01L23/544
CPC分类号： H01L21/78 , H01L21/768
摘要： An energy relieving, redundant crack stop and the method of producing the same is disclosed. The redundant pattern allows the crack propagating energy that is not absorbed by the first ring of metallization to be absorbed by a second area of metallization and also provides a greater surface area over which the crack producing energy may be spread. The redundant crack stop is produced during the metallization process along with the rest of the wiring of the chip surface and, therefore, no additional production steps are necessary to form the structure.
摘要翻译：公开了一种能量消除，冗余裂缝停止及其制造方法。冗余图案允许不被第一金属化环吸收的裂纹传播能量被金属化的第二区域吸收，并且还提供更大的表面积，裂纹产生能量在该表面积上可以扩展。在金属化处理期间，与芯片表面的其余布线一起产生冗余裂纹停止，因此，不需要额外的制造步骤来形成结构。

22. 发明授权

US07642590B2 Semiconductor device and method for making the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07642590B2
公开(公告)日：2010-01-05
申请号：US11942421
申请日：2007-11-19
申请人： Pei-Ing Lee
发明人： Pei-Ing Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L27/10814 , H01L27/10823 , H01L27/10829 , H01L27/10835 , H01L27/10867 , H01L27/10885 , H01L27/10891
摘要： A method for forming a semiconductor device is provided. The method comprises providing a substrate with recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material are formed in spaces between the spacers. The substrate, the spacers and the buried portions are patterned to form parallel shallow trenches for defining buried bit line contacts and capacitor buried surface straps. A layer of dielectric material is formed in the shallow trenches. Word lines are formed across the recessed gates. Bit lines are formed to electrically connect the buried bit line contacts without crossing the capacitor buried surface straps, and stack capacitors are formed to electrically connect with the capacitor buried surface straps. A semiconductor device is also provided.
摘要翻译：提供一种形成半导体器件的方法。该方法包括在其中提供具有凹入栅极和深沟槽电容器器件的衬底。显露了深沟槽电容器器件的凹入栅极和上部的突出。间隔件形成在上部和突起的侧壁上。导电材料的埋入部分形成在间隔件之间的空间中。将衬底，间隔物和掩埋部分图案化以形成用于限定掩埋位线接触和电容器埋入表面带的平行浅沟槽。在浅沟槽中形成介电材料层。字线形成在凹入的门之间。位线被形成为电连接掩埋位线触点而不与电容器埋入表面带交叉，并且形成堆叠电容器以与电容器埋入表面带电连接。还提供了半导体器件。

23. 发明申请

US20090011569A1 ELECTRICAL DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：电气设备及其制造方法
公开(公告)号：US20090011569A1
公开(公告)日：2009-01-08
申请号：US12211815
申请日：2008-09-17
申请人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
发明人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
IPC分类号： H01L21/76
CPC分类号： H01L29/66553 , H01L21/26586 , H01L27/10876 , H01L29/66621 , H01L29/66659
摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.
摘要翻译：公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。多个沟槽嵌入在半导体衬底的存储器阵列区域中。每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

24. 发明授权

US07358133B2 Semiconductor device and method for making the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07358133B2
公开(公告)日：2008-04-15
申请号：US11321156
申请日：2005-12-28
申请人： Pei-Ing Lee
发明人： Pei-Ing Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/10876 , H01L27/10814 , H01L27/10823 , H01L27/10829 , H01L27/10835 , H01L27/10867 , H01L27/10885 , H01L27/10891
摘要： A method for forming a semiconductor device is provided. The method comprises providing a substrate with recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material are formed in spaces between the spacers. The substrate, the spacers and the buried portions are patterned to form parallel shallow trenches for defining buried bit line contacts and capacitor buried surface straps. A layer of dielectric material is formed in the shallow trenches. Word lines are formed across the recessed gates. Bit lines are formed to electrically connect the buried bit line contacts without crossing the capacitor buried surface straps, and stack capacitors are formed to electrically connect with the capacitor buried surface straps. A semiconductor device is also provided.
摘要翻译：提供一种形成半导体器件的方法。该方法包括在其中提供具有凹入栅极和深沟槽电容器器件的衬底。显露了深沟槽电容器器件的凹入栅极和上部的突出。间隔件形成在上部和突起的侧壁上。导电材料的埋入部分形成在间隔件之间的空间中。将衬底，间隔物和掩埋部分图案化以形成用于限定掩埋位线接触和电容器埋入表面带的平行浅沟槽。在浅沟槽中形成介电材料层。字线形成在凹入的门之间。位线被形成为电连接掩埋位线触点而不与电容器埋入表面带交叉，并且形成堆叠电容器以与电容器埋入表面带电连接。还提供了半导体器件。

25. 发明申请

US20080061342A1 SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080061342A1
公开(公告)日：2008-03-13
申请号：US11942421
申请日：2007-11-19
申请人： Pei-Ing Lee
发明人： Pei-Ing Lee
IPC分类号： H01L29/94
CPC分类号： H01L27/10876 , H01L27/10814 , H01L27/10823 , H01L27/10829 , H01L27/10835 , H01L27/10867 , H01L27/10885 , H01L27/10891
摘要： A method for forming a semiconductor device is provided. The method comprises providing a substrate with recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material are formed in spaces between the spacers. The substrate, the spacers and the buried portions are patterned to form parallel shallow trenches for defining buried bit line contacts and capacitor buried surface straps. A layer of dielectric material is formed in the shallow trenches. Word lines are formed across the recessed gates. Bit lines are formed to electrically connect the buried bit line contacts without crossing the capacitor buried surface straps, and stack capacitors are formed to electrically connect with the capacitor buried surface straps. A semiconductor device is also provided.
摘要翻译：提供一种形成半导体器件的方法。该方法包括在其中提供具有凹入栅极和深沟槽电容器器件的衬底。显露了深沟槽电容器器件的凹入栅极和上部的突出。间隔件形成在上部和突起的侧壁上。导电材料的埋入部分形成在间隔件之间的空间中。将衬底，间隔物和掩埋部分图案化以形成用于限定掩埋位线接触和电容器埋入表面带的平行浅沟槽。在浅沟槽中形成介电材料层。字线形成在凹入的门之间。位线被形成为电连接掩埋位线触点而不与电容器埋入表面带交叉，并且形成堆叠电容器以与电容器埋入表面带电连接。还提供了半导体器件。

26. 发明授权

US07316978B2 Method for forming recesses 有权
标题翻译：凹槽形成方法
公开(公告)号：US07316978B2
公开(公告)日：2008-01-08
申请号：US11195294
申请日：2005-08-02
申请人： Pei-Ing Lee , Chung-Yuan Lee , Chien-Li Cheng
发明人： Pei-Ing Lee , Chung-Yuan Lee , Chien-Li Cheng
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/26586 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L29/66621 , Y10S438/944 , Y10S438/947
摘要： A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the protrusions, tilt implanting the mask layer using a first implanting mask adjacent to the first side wall of the protrusions, removing implanted portions of the mask layer to form a patterned mask layer, and etching the substrate using the patterned mask layer, thereby forming a recess.
摘要翻译：一种形成凹部的方法。该方法包括提供具有两个突起的基底，该突起具有第一侧壁和与设置在基底上方的第一侧壁相对的第二侧壁，在基底上保形地形成掩模层和突起，使用第一将掩模与所述突起的第一侧壁相邻地植入，去除所述掩模层的注入部分以形成图案化掩模层，并且使用所述图案化掩模层蚀刻所述衬底，从而形成凹部。

27. 发明申请

US20070161205A1 ELECTRICAL DEVICE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：电气设备及其制造方法
公开(公告)号：US20070161205A1
公开(公告)日：2007-07-12
申请号：US11556170
申请日：2006-11-03
申请人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
发明人： Shian-Jyh Lin , Chien-Li Cheng , Pei-Ing Lee , Chung-Yuan Lee
IPC分类号： H01L21/76
CPC分类号： H01L29/66553 , H01L21/26586 , H01L27/10876 , H01L29/66621 , H01L29/66659
摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.
摘要翻译：公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。多个沟槽嵌入在半导体衬底的存储器阵列区域中。每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

28. 发明申请

US20070161179A1 Semiconductor device and method for making the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070161179A1
公开(公告)日：2007-07-12
申请号：US11321156
申请日：2005-12-28
申请人： Pei-Ing Lee
发明人： Pei-Ing Lee
IPC分类号： H01L21/8242
CPC分类号： H01L27/10876 , H01L27/10814 , H01L27/10823 , H01L27/10829 , H01L27/10835 , H01L27/10867 , H01L27/10885 , H01L27/10891
摘要： A method for forming a semiconductor device is provided. The method comprises providing a substrate with recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material are formed in spaces between the spacers. The substrate, the spacers and the buried portions are patterned to form parallel shallow trenches for defining buried bit line contacts and capacitor buried surface straps. A layer of dielectric material is formed in the shallow trenches. Word lines are formed across the recessed gates. Bit lines are formed to electrically connect the buried bit line contacts without crossing the capacitor buried surface straps, and stack capacitors are formed to electrically connect with the capacitor buried surface straps. A semiconductor device is also provided.
摘要翻译：提供一种形成半导体器件的方法。该方法包括在其中提供具有凹入栅极的衬底和其中的深沟槽电容器器件。显露了深沟槽电容器器件的凹入栅极和上部的突出。间隔件形成在上部和突起的侧壁上。导电材料的埋入部分形成在间隔件之间的空间中。将衬底，间隔物和掩埋部分图案化以形成用于限定掩埋位线接触和电容器埋入表面带的平行浅沟槽。在浅沟槽中形成介电材料层。字线形成在凹入的门之间。位线被形成为电连接掩埋位线触点而不与电容器埋入表面带交叉，并且形成堆叠电容器以与电容器埋入表面带电连接。还提供了半导体器件。

29. 发明授权

US07179748B1 Method for forming recesses 有权
标题翻译：凹槽形成方法
公开(公告)号：US07179748B1
公开(公告)日：2007-02-20
申请号：US11195293
申请日：2005-08-02
申请人： Pei-Ing Lee , Chung-Yuan Lee , Chien-Li Cheng
发明人： Pei-Ing Lee , Chung-Yuan Lee , Chien-Li Cheng
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/26586 , H01L27/10823 , H01L27/10829 , H01L27/10876 , H01L29/66621 , Y10S438/944 , Y10S438/947
摘要： A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the protrusions, tilt implanting the mask layer with a first angle using a first implanting mask adjacent to the first side wall of the protrusions, tilt implanting the mask layer with a second angle using a second implanting mask adjacent to the second side wall of the protrusions, removing implanted portions of the mask layer to form a patterned mask layer, and etching the substrate using the patterned mask layer, thereby forming a recess, wherein distances from the recess to the two protrusions, respectively, are different.
摘要翻译：一种形成凹部的方法。该方法包括提供具有两个突出物的两个突起，所述两个突起具有第一侧壁和与设置在基底上方的第一侧壁相对的第二侧壁，在基底上共形成掩模层和突起，倾斜地将掩模层以第一使用与突起的第一侧壁相邻的第一注入掩模的角度，使用与突起的第二侧壁相邻的第二注入掩模以第二角度注入掩模层，去除掩模层的植入部分以形成图案化掩模层，并使用图案化掩模层蚀刻基板，从而形成凹部，其中分别从凹部到两个突起的距离不同。

30. 发明申请

US20060270176A1 Method for forming a semiconductor device 有权
标题翻译：半导体器件形成方法
公开(公告)号：US20060270176A1
公开(公告)日：2006-11-30
申请号：US11140889
申请日：2005-05-31
申请人： Pei-Ing Lee , Chung-Yuan Lee , Chien-Li Cheng
发明人： Pei-Ing Lee , Chung-Yuan Lee , Chien-Li Cheng
IPC分类号： H01L21/20
CPC分类号： H01L29/66621 , H01L27/10823 , H01L27/10829 , H01L27/1087 , H01L27/10876
摘要： A method for forming a semiconductor device. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor is formed in each trench. A protrusion is formed on each deep trench capacitor, wherein a top surface level of each protrusion is higher than that of the pad layer. Spacers are formed on sidewalls of the protrusions, and the pad layer and the substrate are etched using the spacers and the protrusions as a mask to form a recess. A recessed gate is formed in the recess.
摘要翻译：一种形成半导体器件的方法。提供其上具有垫层的衬底。图案化衬垫层和衬底以形成至少两个沟槽。在每个沟槽中形成深沟槽电容器。在每个深沟槽电容器上形成突起，其中每个突起的顶表面水平高于焊盘层的顶表面高度。间隔件形成在突起的侧壁上，并且使用间隔件和突起作为掩模来蚀刻衬垫层和衬底以形成凹部。在凹部中形成凹槽。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式