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21. 发明申请

US20120117333A1 CRITICAL SECTION DETECTION AND PREDICTION MECHANISM FOR HARDWARE LOCK ELISION 审中-公开
标题翻译：硬件锁定的关键部分检测和预测机制
公开(公告)号：US20120117333A1
公开(公告)日：2012-05-10
申请号：US13350572
申请日：2012-01-13
申请人： Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan
发明人： Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan
IPC分类号： G06F12/08
CPC分类号： G06F9/3865 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3842 , G06F9/528
摘要： A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock instruction is detected with detection logic, which potentially resides in decode logic. A lock instruction entry associated with the lock instruction is stored/created. Address locations and values to be written to those address location of subsequent potential lock release instruction are compared to the address loaded from by the lock instruction and the value load by the lock instruction. If the addresses and values match, it is determined that the lock release instruction matches the lock instruction. A prediction entry stores a reference to the lock instruction, such as a last instruction pointer (LIP), and an associated value to represent the lock instruction is to be elided upon subsequent detection, if it is determined that the lock release instruction matches the lock instruction.
摘要翻译：这里描述了用于检测锁定指令和锁定释放指令以及预测关键部分的方法和装置。检测逻辑检测到锁定指令，这可能存在于解码逻辑中。存储/创建与锁定指令相关联的锁定指令条目。将要写入后续潜在锁定释放指令的地址位置的地址位置和值与通过锁定指令加载的地址和锁定指令的值负载进行比较。如果地址和值匹配，则确定锁定释放指令与锁定指令匹配。预测条目存储对诸如最后指令指针（LIP）的锁定指令的引用，并且如果确定锁定解除指令与锁定相匹配，则在后续检测时将要消除表示锁定指令的关联值指令。

22. 发明授权

US07900023B2 Technique to enable store forwarding during long latency instruction execution 有权
标题翻译：在长时间延迟指令执行期间允许存储转发的技术
公开(公告)号：US07900023B2
公开(公告)日：2011-03-01
申请号：US11015874
申请日：2004-12-16
申请人： Ravi Rajwar , Srikanth T. Srinivasan , Haitham Akkary , Amit Gandhi
发明人： Ravi Rajwar , Srikanth T. Srinivasan , Haitham Akkary , Amit Gandhi
IPC分类号： G06F9/30
CPC分类号： G06F9/3826 , G06F9/3834 , G06F9/3836
摘要： A technique to allow independent loads to be satisfied during high-latency instruction processing. Embodiments of the invention relate to a technique in which a storage structure is used to hold store operations in program order while independent load instructions are satisfied during a time in which a high-latency instruction is being processed. After the high-latency instruction is processed, the store operations can be restored in program order without searching the storage structure.
摘要翻译：允许在高延迟指令处理期间满足独立负载的技术。本发明的实施例涉及一种技术，其中存储结构用于以程序顺序保持存储操作，而在处理高延迟指令的时间期间满足独立的加载指令。处理高延迟指令后，可以按程序顺序恢复存储操作，而无需搜索存储结构。

23. 发明授权

US07487337B2 Back-end renaming in a continual flow processor pipeline 有权
标题翻译：在持续流处理器管道中进行后端重命名
公开(公告)号：US07487337B2
公开(公告)日：2009-02-03
申请号：US10953761
申请日：2004-09-30
申请人： Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan
发明人： Haitham Akkary , Ravi Rajwar , Srikanth T. Srinivasan
IPC分类号： G06F9/30 , G06F15/00
CPC分类号： G06F9/3842 , G06F9/384
摘要： Embodiments of the present invention relate to a system and method for comparatively increasing processor throughput and relieving pressure on the processor's scheduler and register file by diverting instructions dependent on long-latency operations from a flow of the processor pipeline and re-introducing the instructions into the flow when the long-latency operations are completed. In this way, the instructions do not tie up resources and overall instruction throughput in the pipeline is comparatively increased. Before the instructions are diverted from the pipeline, they may undergo a conventional process to map logical registers of the instructions to physical registers. Before the instructions are re-introduced into the pipeline, the physical registers mapped according to the conventional process may be re-mapped to other physical registers, thereby efficiently preserving correct program sequence information.
摘要翻译：本发明的实施例涉及一种用于相对增加处理器吞吐量并减轻处理器调度器和寄存器文件上的压力的系统和方法，该方法通过根据来自处理器流水线的长度等待时间操作转移指令，并将指令重新引入到长时间延迟操作完成时流量。以这种方式，指令不会占用资源，并且管道中的总体指令吞吐量相对增加。在指令从流水线转移之前，它们可以经历常规过程，将指令的逻辑寄存器映射到物理寄存器。在将指令重新引入到流水线之前，根据常规过程映射的物理寄存器可以重新映射到其他物理寄存器，从而有效地保留正确的程序序列信息。

24. 发明申请

US20060277398A1 Method and apparatus for instruction latency tolerant execution in an out-of-order pipeline 审中-公开
标题翻译：用于在无序流水线中执行指令等待时间的方法和装置
公开(公告)号：US20060277398A1
公开(公告)日：2006-12-07
申请号：US11145409
申请日：2005-06-03
申请人： Haitham Akkary , Ravi Rajwar , Srikanth Srinivasan , Christopher Wilkerson
发明人： Haitham Akkary , Ravi Rajwar , Srikanth Srinivasan , Christopher Wilkerson
IPC分类号： G06F9/44
CPC分类号： G06F9/3836 , G06F9/3814 , G06F9/383 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A method and apparatus for setting aside a long-latency micro-operation from a reorder buffer is disclosed. In one embodiment, a long-latency micro-operation would conventionally stall a reorder buffer. Therefore a secondary buffer may be used to temporarily store that long-latency micro-operation, and other micro-operations depending from it, until that long-latency micro-operation is ready to execute. These micro-operations may then be reintroduced into the reorder buffer for execution. The use of poisoned bits may be used to ensure correct retirement of register values merged from both pre- and post-execution of the micro-operations which were set aside in the secondary buffer.
摘要翻译：公开了一种用于从重排序缓冲器中排除长延迟微操作的方法和装置。在一个实施例中，长时间延迟微操作通常会阻止重新排序缓冲器。因此，可以使用辅助缓冲器来临时存储长延迟微操作以及依赖于其的微操作，直到长时间延迟微操作准备好执行。然后可以将这些微操作重新引入重排序缓冲器中以供执行。可以使用中毒的位来确保正确地退出从辅助缓冲器中放置的微操作执行之前和之后合并的寄存器值。

25. 发明申请

US20160132336A1 Method, apparatus, and system for speculative abort control mechanisms 审中-公开
公开(公告)号：US20160132336A1
公开(公告)日：2016-05-12
申请号：US14998276
申请日：2015-12-26
申请人： Martin G. Dixon , Ravi Rajwar , Konrad K. Lai , Robert S. Chappell , Rajesh S. Parthasarathy , Alexandre J. Farcy , Ilhyun Kim , Prakash Math , Matthew Merten , Vijaykumar Kadgi
发明人： Martin G. Dixon , Ravi Rajwar , Konrad K. Lai , Robert S. Chappell , Rajesh S. Parthasarathy , Alexandre J. Farcy , Ilhyun Kim , Prakash Math , Matthew Merten , Vijaykumar Kadgi
IPC分类号： G06F9/30 , G06F12/08 , G06F13/42 , G06F13/16 , G06F13/40
CPC分类号： G06F9/3855 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/3859 , G06F9/3861 , G06F9/467 , G06F9/528 , G06F12/0806 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F12/0895 , G06F12/0897 , G06F12/1027 , G06F12/1045 , G06F13/1673 , G06F13/4068 , G06F13/4282 , G06F2212/452 , G06F2212/50 , G06F2212/60 , G06F2212/602 , G06F2212/621 , G06F2212/68 , G06F2212/682
摘要： An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software. And to enable testing of such a fallback path, in one implementation, hardware provides software a mechanism to always abort speculative code regions.

26. 发明授权

US08972994B2 Method and apparatus to bypass object lock by speculative execution of generated bypass code shell based on bypass failure threshold in managed runtime environment 有权
标题翻译：在托管运行时环境中基于旁路故障阈值的推测执行生成的旁路代码shell来绕过对象锁的方法和装置
公开(公告)号：US08972994B2
公开(公告)日：2015-03-03
申请号：US12645668
申请日：2009-12-23
申请人： Suresh Srinivas , Stephen H. Dohrmann , Mingqiu Sun , Uma Srinivasan , Ravi Rajwar , Konrad K. Lai
发明人： Suresh Srinivas , Stephen H. Dohrmann , Mingqiu Sun , Uma Srinivasan , Ravi Rajwar , Konrad K. Lai
IPC分类号： G06F9/44 , G06F9/46 , G06F9/52 , G06F9/455 , G06F17/30 , G06F9/38 , G06F9/45
CPC分类号： G06F9/528 , G06F8/458 , G06F9/3842 , G06F9/45516 , G06F9/526 , G06F17/30168 , G06F17/30362 , Y10S707/99938
摘要： Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes receiving an object lock request from a processor, the lock request associated with object lock code to lock an object, and generating object lock-bypass code based on a type of the processor, the object lock-bypass code to execute in a managed runtime in response to receiving the object lock request. The example method also includes identifying a type of instruction set architecture (ISA) associated with the processor, invoking a checkpoint instruction for the processor based on the identified ISA, suspending the object lock code from executing and executing target code when the object is uncontended, and allowing the object lock code to execute when the object is contended.
摘要翻译：公开了用于管理对象锁的示例性方法和装置。所公开的示例性方法包括从处理器接收对象锁定请求，与对象锁定代码相关联的锁定请求以锁定对象，以及基于处理器的类型生成对象锁定旁路代码，执行对象锁定旁路代码在受管运行时响应于接收到对象锁定请求。示例性方法还包括识别与处理器相关联的指令集架构（ISA）的类型，基于所识别的ISA调用处理器的检查点指令，当对象不受约束时暂停对象锁定代码执行和执行目标代码，并允许对象锁定代码在对象被竞争时执行。

27. 发明申请

US20140379996A1 METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL INSTRUCTIONS 审中-公开
标题翻译：方法，装置和系统的交互式分析控制指令
公开(公告)号：US20140379996A1
公开(公告)日：2014-12-25
申请号：US13997245
申请日：2012-02-02
申请人： Ravi Rajwar , Martin G. Dixon , Konrad K. Lai , Robert S. Chappell , Bret L. Toll
发明人： Ravi Rajwar , Martin G. Dixon , Konrad K. Lai , Robert S. Chappell , Bret L. Toll
IPC分类号： G06F9/52 , G06F12/08 , G06F9/46
摘要： An apparatus and method is described herein for providing speculative escape instructions. Specifically, an explicit non-transactional load operation is described herein. During execution of a speculative code region (e.g. a transaction or critical section) loads are normally tracked in a read set. However, a programmer or compiler may utilize the explicit non-transactional read to load from a memory address into a destination register, while not adding the read/load to the transactional read set. Similarly, a non-transactional store is also provided. Here, a transactional store is performed and not added to a write set during speculative code execution. And the store may be immediately globally visible and/or persistent (even after an abort of the speculative code region). In other words, speculative escape operations are provided to ‘escape’ a speculative code region to perform non-transactional memory accesses without causing the speculative code region to abort or fail.
摘要翻译：这里描述了一种用于提供推测逃逸指令的装置和方法。具体地，本文描述了显式的非事务性加载操作。在推测性代码区域（例如交易或关键部分）的执行期间，通常在读取集合中跟踪负载。然而，程序员或编译器可以利用显式的非事务性读取从存储器地址加载到目标寄存器中，而不将读取/加载添加到事务读取集合。同样，也提供非事务存储。这里，在推测性代码执行期间执行事务存储并且不添加到写入集合。并且商店可能立即全局可见和/或持久（即使在推测性代码区域中止之后）。换句话说，提供推测性逃避操作以“逃逸”推测性代码区域以执行非事务性存储器访问，而不会导致推测性代码区域中止或失败。

28. 发明授权

US08881106B2 Debugging parallel software using speculatively executed code sequences in a multiple core environment 有权
标题翻译：在多核心环境中使用推测性执行的代码序列来调试并行软件
公开(公告)号：US08881106B2
公开(公告)日：2014-11-04
申请号：US12978480
申请日：2010-12-24
申请人： Peter Lachner , Konrad K. Lai , Ravi Rajwar
发明人： Peter Lachner , Konrad K. Lai , Ravi Rajwar
IPC分类号： G06F9/44 , G06F11/36 , G06F9/38
CPC分类号： G06F9/3842 , G06F9/3861 , G06F11/362
摘要： Methods and apparatus relating to debugging parallel software using speculatively executed code sequences in a multiple core environment are described. In an embodiment, occurrence of a speculative code debug event is detected and a speculative code execution debug module is executed in response to occurrence of the event. Other embodiments are also disclosed and claimed.
摘要翻译：描述了在多核心环境中使用推测执行的代码序列调试并行软件的方法和装置。在一个实施例中，检测到推测代码调试事件的发生，并且响应于事件的发生而执行推测代码执行调试模块。还公开并要求保护其他实施例。

29. 发明申请

US20110225375A1 Concurrent Execution of Critical Sections by Eliding Ownership of Locks 审中-公开
标题翻译：通过确定锁定所有权并行执行关键部分
公开(公告)号：US20110225375A1
公开(公告)日：2011-09-15
申请号：US13113432
申请日：2011-05-23
申请人： Ravi Rajwar , James R. Goodman
发明人： Ravi Rajwar , James R. Goodman
IPC分类号： G06F12/00
CPC分类号： G06F9/528 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/3009 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/52 , G06F12/0808 , G06F12/0844 , G06F12/0891 , G06F12/12 , G06F12/128 , G06F12/1458 , G06F12/1475 , G06F2212/1041 , G06F2212/1052 , G06F2212/283 , G06F2212/62
摘要： One embodiment of the present invention provides a system that facilitates avoiding locks by speculatively executing critical sections of code. During operation, the system allows a process to speculatively execute a critical section of code within a program without first acquiring a lock associated with the critical section. If the process subsequently completes the critical section without encountering an interfering data access from another process, the system commits changes made during the speculative execution, and resumes normal non-speculative execution of the program past the critical section. Otherwise, if an interfering data access from another process is encountered during execution of the critical section, the system discards changes made during the speculative execution, and attempts to re-execute the critical section.
摘要翻译：本发明的一个实施例提供一种通过推测性地执行代码的关键部分来有助于避免锁定的系统。在操作期间，系统允许进程在程序中推测性地执行代码的关键部分而不首先获得与关键部分相关联的锁定。如果该过程随后完成关键部分而没有遇到来自另一进程的干扰数据访问，则系统进行在推测执行期间所做的更改，并且通过关键部分恢复程序的正常非推测性执行。否则，如果在执行关键部分期间遇到来自其他进程的干扰数据访问，则系统将丢弃在推测执行期间所做的更改，并尝试重新执行临界部分。

30. 发明申请

US20110161639A1 Event counter checkpointing and restoring 有权
标题翻译：事件计数器检查和恢复
公开(公告)号：US20110161639A1
公开(公告)日：2011-06-30
申请号：US12655204
申请日：2009-12-26
申请人： Laura A. Knauth , Ravi Rajwar , Konrad K. Lai , Martin G. Dixon , Peggy Irelan
发明人： Laura A. Knauth , Ravi Rajwar , Konrad K. Lai , Martin G. Dixon , Peggy Irelan
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F11/1469 , G06F9/3861 , G06F9/3863 , G06F9/466 , G06F11/1451 , G06F11/3466 , G06F2201/82 , G06F2201/84 , G06F2201/86 , G06F2201/87 , G06F2201/88
摘要： A method of one aspect may include storing an event count of an event counter that counts events that occur during execution within a logic device. The method may further include restoring the event counter to the stored event count after the event counter has counted additional events. Other methods are also disclosed. Apparatus, systems, and machine-readable medium having software are also disclosed.
摘要翻译：一个方面的方法可以包括存储事件计数器的事件计数器，其计数在逻辑设备内执行期间发生的事件。该方法还可以包括在事件计数器计数附加事件之后恢复事件计数器到所存储的事件计数。还公开了其它方法。还公开了具有软件的装置，系统和机器可读介质。

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